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hcs08 microcontrollers freescale.com MC9S08JM16 mc9s08jm8 data sheet MC9S08JM16 rev. 2 5/2008

MC9S08JM16 series features 8-bit hcs08 central processor unit (cpu) ? 48 mhz hcs08 cpu (central processor unit) ? 24 mhz internal bus frequency ? hc08 instruction set with added bgnd instruction ? background debugging system ? breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) ? in-circuit emulator (ice) debug module containing two comparators and nine trigger modes. eight deep fifo for storing change-of-flow addresses and event-only data. debug module supports both tag and force breakpoints ? support for up to 32 interrupt/reset sources memory options ? up to 16 kb of on-chip in-circuit programmable flash memory with block protection and security options ? up to 1 kb of on-chip ram ? 256 bytes of usb ram clock source options ? clock source options include crystal, resonator, external clock ? mcg (multi-purpose clock generator) ? pll and fll; internal reference clock with trim adjustment system protection ? optional computer operating properly (cop) reset with option to run from independent 1 khz internal clock source or the bus clock ? low-voltage detection with reset or interrupt ? illegal opcode detection with reset ? illegal address detection with reset power-saving modes ? wait plus two stops peripherals ? usb ? usb 2.0 full-speed (12 mbps) with dedicated on-chip 3.3 v regulator and transceiver; supporting endpoint 0 and up to 6 additional endpoints ? adc ? 8-channel, 12-bit analog-to-digital converter with automatic compare function; internal temperature sensor ? acmp ? analog comparator with option to compare to internal reference; operation in stop3 mode ? sci ? up to two serial communications interface modules with optional 13-bit break; lin extensions ? spi ? two 8- or 16-bit selectable serial peripheral interface modules with a receive data buffer hardware match function ? iic ? inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; multi-master op eration; programmable slave address; interrupt-driven byte-by-byte data transfer; broadcast mode; 10-bit addressing ? timers ? one 2-channel and one 4-channel 16-bit timer/pulse-width modulator (tpm) modules; selectable input capture, output compare, and edge-alig ned pwm capability on each channel. each timer module may be configured for buffered, centered pwm (cpwm) on all channels ? kbi ? 7-pin keyboard interrupt module ? rtc ? real-time counter with binary- or decimal-based prescaler input/output ? up to 37 general purpose input/output pins ? software selectable pullup on ports when used as inputs ? software selectable slew rate control on ports when used as outputs ? software selectable drive strength on ports when used as outputs ? master reset pin and power-on reset (por) ? internal pullup on reset , irq, and bkgd/ms pins to reduce customer system cost package options ? 48-pin quad flat no-lead (qfn) ? 44-pin low-profile quad flat package (lqfp) ? 32-pin low-profile quad flat package (lqfp)

MC9S08JM16 data sheet covers: MC9S08JM16 mc9s08jm8 MC9S08JM16 rev. 2 5/2008
MC9S08JM16 series data sheet, rev. 2 6 freescale semiconductor revision history to provide the most up-to-date information, the ve rsion of this document on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision number revision date description of changes rev. 1 3/2008 initial release. rev. 2 5/2008 added emc data in appendix. this product incorporates superflash ? technology licensed from sst. freescale? and the freescale logo are trade marks of freescale semiconductor, inc. ? freescale semiconductor, inc., 2008. all rights reserved.
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 7 list of chapters chapter number title page chapter 1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 chapter 2 pins and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 chapter 3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 chapter 4 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 chapter 5 resets, interrupts, and system co nfiguration . . . . . . . . . . . . . . . 61 chapter 6 parallel input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 chapter 7 central processor unit (s08cpuv2) . . . . . . . . . . . . . . . . . . . . . . . 99 chapter 8 keyboard interrupt (s 08kbiv2) . . . . . . . . . . . . . . . . . . . . . . . . . . 119 chapter 9 5 v analog comparator (s08acmpv2 ) . . . . . . . . . . . . . . . . . . . . 127 chapter 10 analog-to-digital converter (s08 adc12v1) . . . . . . . . . . . . . . . 133 chapter 11 inter-integrated circuit (s08iicv2) . . . . . . . . . . . . . . . . . . . . . . . 159 chapter 12 multi-purpose clock generator (s08mcgv1) . . . . . . . . . . . . . . 177 chapter 13 real-time counter (s08rtcv1) . . . . . . . . . . . . . . . . . . . . . . . . . 209 chapter 14 serial communications interfa ce (s08sciv4) . . . . . . . . . . . . . . 219 chapter 15 16-bit serial peripheral interf ace (s08spi16v1) . . . . . . . . . . . . 239 chapter 16 timer/pulse-width modulator (s08t pmv2) . . . . . . . . . . . . . . . . 267 chapter 17 universal serial bus device controller (s08usbv1) . . . . . . . . 295 chapter 18 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 appendix a electrical characteri stics.......................... ........................ ......... 349 appendix b ordering information an d mechanical draw ings..................... 373

MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 9 contents section number title page chapter 1 device overview 1.1 introducti on ............................................................................................................... ......................19 1.2 mcu block diagram .......................................................................................................... ............19 1.3 system clock di stribution .................................................................................................. ............21 chapter 2 pins and connections 2.1 introducti on ............................................................................................................... ......................23 2.2 device pin assi gnment ...................................................................................................... .............23 2.3 recommended system connections ............................................................................................. ..25 2.3.1 power (v dd , v ss , v ssosc , v ddad , v ssad , v usb33 ) ....................................................27 2.3.2 oscillator (xtal, extal) ..............................................................................................27 2.3.3 reset pin ........................................................................................................................28 2.3.4 background/mode select (bkgd/ms) ............................................................................28 2.3.5 adc reference pins (v refh , v refl ) .............................................................................28 2.3.6 external interrupt pin (irq) ............................................................................................. 28 2.3.7 usb data pins (usbdp, usbdn) ...................................................................................29 2.3.8 general-purpose i/o and peripheral ports ........................................................................29 chapter 3 modes of operation 3.1 introducti on ............................................................................................................... ......................31 3.2 features ................................................................................................................... ........................31 3.3 run mode ................................................................................................................... .....................31 3.4 active backgr ound mode ..................................................................................................... ..........31 3.5 wait mode .................................................................................................................. .....................32 3.6 stop modes ................................................................................................................. .....................33 3.6.1 stop3 mode ............................................................................................................... ........33 3.6.2 stop2 mode ............................................................................................................... ........34 3.6.3 on-chip peripheral modules in stop modes ....................................................................35 chapter 4 memory 4.1 MC9S08JM16 series memory map ............................................................................................... 37 4.1.1 reset and interrupt vect or assignments ...........................................................................39 4.2 register addresses a nd bit assignments ..................................................................................... ...40 4.3 ram (system ram) ........................................................................................................... ...........46 4.4 usb ram .................................................................................................................... ...................47
MC9S08JM16 series data sheet, rev. 2 10 freescale semiconductor 4.5 flash ...................................................................................................................... ..........................47 4.5.1 features ................................................................................................................. ............47 4.5.2 program and erase times .................................................................................................4 7 4.5.3 program and erase command execution .........................................................................48 4.5.4 burst program ex ecution .................................................................................................. 49 4.5.5 access erro rs ............................................................................................................ ........51 4.5.6 flash block pr otection ................................................................................................... ...52 4.5.7 vector redire ction ....................................................................................................... .....53 4.6 security ................................................................................................................... .........................53 4.7 flash registers and control bits ........................................................................................... ..........54 4.7.1 flash clock divider re gister (fcdiv) ............................................................................55 4.7.2 flash options register (fopt and nvopt) ....................................................................56 4.7.3 flash configuration register (fcnfg) ...........................................................................57 4.7.4 flash protection register (fprot and nvprot) ..........................................................57 4.7.5 flash status register (fstat) ..........................................................................................58 4.7.6 flash command register (fcmd) ...................................................................................59 chapter 5 resets, interrupts, and system configuration 5.1 introducti on ............................................................................................................... ......................61 5.2 features ................................................................................................................... ........................61 5.3 mcu reset .................................................................................................................. ....................61 5.4 computer operating prope rly (cop) watchdog .............................................................................62 5.5 interrupts ................................................................................................................. ........................63 5.5.1 interrupt stack frame .................................................................................................... ...64 5.5.2 external interrupt re quest (irq) pin ...............................................................................64 5.5.3 interrupt vectors, sources , and local ma sks ...................................................................65 5.6 low-voltage detect (lvd) system ............................................................................................ ....67 5.6.1 power-on reset op eration ...............................................................................................67 5.6.2 lvd reset oper ation ...................................................................................................... ..67 5.6.3 lvd interrupt op eration .................................................................................................. .68 5.6.4 low-voltage warning (lvw) ...........................................................................................68 5.7 reset, interrupt, and system contro l registers and control bits ...................................................68 5.7.1 interrupt pin request status and control register (irqsc) ............................................68 5.7.2 system reset status register (srs) .................................................................................69 5.7.3 system background debug force re set register (sbdfr) ............................................70 5.7.4 system options register 1 (sopt1) ................................................................................71 5.7.5 system options register 2 (sopt2) ................................................................................72 5.7.6 system device identification register (sdidh, sdidl) ................................................73 5.7.7 system power management status a nd control 1 register (spmsc1) ...........................74 5.7.8 system power management status a nd control 2 register (spmsc2) ...........................75 chapter 6 parallel input/output 6.1 introducti on ............................................................................................................... ......................77
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 11 6.2 port data and data directio n ............................................................................................... ...........78 6.3 pin control ................................................................................................................ ......................79 6.3.1 internal pullup enable ................................................................................................... ...79 6.3.2 output slew rate c ontrol enable .....................................................................................79 6.3.3 output drive strength select ............................................................................................7 9 6.4 pin behavior in stop modes ................................................................................................. ...........79 6.5 parallel i/o and pin control regi sters ..................................................................................... .......80 6.5.1 port a i/o registers (ptad and ptadd) ........................................................................80 6.5.2 port a pin control registers (ptape, ptase, ptads) .................................................81 6.5.3 port b i/o registers (ptbd and ptbdd) ........................................................................82 6.5.4 port b pin control registers (ptbpe, ptbse, ptbds) .................................................83 6.5.5 port c i/o registers (ptcd and ptcdd) ........................................................................84 6.5.6 port c pin control registers (ptcpe, ptcse, ptcds) .................................................85 6.5.7 port d i/o registers (ptdd and ptddd) .......................................................................87 6.5.8 port d pin control registers (ptdpe, ptdse, ptdds) ................................................88 6.5.9 port e i/o registers (pted and ptedd) ........................................................................89 6.5.10 port e pin control registers (ptepe, ptese, pteds) ..................................................91 6.5.11 port f i/o registers (p tfd and ptfdd) .........................................................................92 6.5.12 port f pin control register s (ptfpe, ptfse, ptfds) ...................................................93 6.5.13 port g i/o registers (ptgd and ptgdd) .......................................................................95 6.5.14 port g pin control registers (ptgpe, ptgse, ptgds) ................................................96 chapter 7 central processor unit (s08cpuv2) 7.1 introducti on ............................................................................................................... ......................99 7.1.1 features ................................................................................................................. ............99 7.2 programmer?s model and cpu registers .....................................................................................10 0 7.2.1 accumulator (a) .......................................................................................................... ...100 7.2.2 index register (h:x) ..................................................................................................... .100 7.2.3 stack pointer (sp) ....................................................................................................... ....101 7.2.4 program counter (pc) ....................................................................................................1 01 7.2.5 condition code register (ccr) .....................................................................................101 7.3 addressing modes ........................................................................................................... ..............103 7.3.1 inherent addressing mode (inh) ...................................................................................103 7.3.2 relative addressing mode (rel) ..................................................................................103 7.3.3 immediate addressing mode (imm) ..............................................................................103 7.3.4 direct addressing mode (dir) ......................................................................................103 7.3.5 extended addressing mode (ext) ................................................................................104 7.3.6 indexed addressing mode ..............................................................................................104 7.4 special oper ations ......................................................................................................... ................105 7.4.1 reset seque nce ........................................................................................................... ....105 7.4.2 interrupt sequence ....................................................................................................... ...105 7.4.3 wait mode op eration ...................................................................................................... 106 7.4.4 stop mode oper ation ...................................................................................................... 106 7.4.5 bgnd instru ction ......................................................................................................... ..107
MC9S08JM16 series data sheet, rev. 2 12 freescale semiconductor 7.5 hcs08 instruction set summary .............................................................................................. ....108 chapter 8 keyboard interrupt (s08kbiv2) 8.1 introducti on ............................................................................................................... ....................119 8.1.1 features ................................................................................................................. ..........121 8.1.2 modes of oper ation ....................................................................................................... .121 8.1.3 block diag ram ............................................................................................................ ....121 8.2 external signal de scription ................................................................................................ ..........122 8.3 register definition ........................................................................................................ ................122 8.3.1 kbi status and control register (kbisc) .....................................................................122 8.3.2 kbi pin enable register (kbipe) ..................................................................................123 8.3.3 kbi edge select register (kbies) ................................................................................123 8.4 functional description ..................................................................................................... .............124 8.4.1 edge only sens itivity .................................................................................................... .124 8.4.2 edge and level se nsitivity .............................................................................................12 4 8.4.3 kbi pullup/pulldown resistors ......................................................................................125 8.4.4 kbi initiali zation ....................................................................................................... .....125 chapter 9 5 v analog comparator (s08acmpv2) 9.1 introducti on ............................................................................................................... ....................127 9.1.1 acmp configuration information ..................................................................................127 9.1.2 acmp/tpm configurati on information ........................................................................127 9.1.3 features ................................................................................................................. ..........129 9.1.4 modes of oper ation ....................................................................................................... .129 9.1.5 block diag ram ............................................................................................................ ....129 9.2 external signal de scription ................................................................................................ ..........130 9.3 memory map ................................................................................................................ ................130 9.3.1 register descri ptions .................................................................................................... ..130 9.4 functional description ..................................................................................................... .............132 chapter 10 analog-to-digital converter (s08adc12v1) 10.1 overview .................................................................................................................. .....................133 10.1.1 module configur ations ................................................................................................... 133 10.1.2 low-power mode operation ..........................................................................................135 10.1.3 features ................................................................................................................ ...........137 10.1.4 adc module block diagram .........................................................................................137 10.2 external signal de scription ............................................................................................... ...........138 10.2.1 analog power (v ddad ) ..................................................................................................139 10.2.2 analog ground (v ssad ) .................................................................................................139 10.2.3 voltage reference high (v refh ) ...................................................................................139 10.2.4 voltage reference low (v refl ) ....................................................................................139 10.2.5 analog channel inputs (adx) ........................................................................................139
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 13 10.3 register definition ....................................................................................................... .................139 10.3.1 status and control regi ster 1 (adcsc1) ......................................................................139 10.3.2 status and control regi ster 2 (adcsc2) ......................................................................141 10.3.3 data result high register (adcrh) .............................................................................141 10.3.4 data result low regi ster (adcrl) ..............................................................................142 10.3.5 compare value high register (adccvh) ....................................................................142 10.3.6 compare value low register (adccvl) .....................................................................143 10.3.7 configuration regist er (adccfg) ................................................................................143 10.3.8 pin control 1 regist er (apctl1) ..................................................................................144 10.3.9 pin control 2 regist er (apctl2) ..................................................................................145 10.3.10pin control 3 regist er (apctl3) ..................................................................................146 10.4 functional description .................................................................................................... ..............147 10.4.1 clock select and di vide control ....................................................................................147 10.4.2 input select and pin control ...........................................................................................1 48 10.4.3 hardware trigger ........................................................................................................ ....148 10.4.4 conversion c ontrol ...................................................................................................... ...148 10.4.5 automatic compare function .........................................................................................151 10.4.6 mcu wait mode op eration ............................................................................................151 10.4.7 mcu stop3 mode operation ..........................................................................................151 10.4.8 mcu stop2 mode operation ..........................................................................................152 10.5 initialization in formation ................................................................................................ ..............152 10.5.1 adc module initializa tion example .............................................................................153 10.6 application information ................................................................................................... .............154 10.6.1 external pins and routing ..............................................................................................1 54 10.6.2 sources of error ........................................................................................................ ......156 chapter 11 inter-integrated circuit (s08iicv2) 11.1 introducti on .............................................................................................................. .....................159 11.1.1 features ................................................................................................................ ...........161 11.1.2 modes of op eration ...................................................................................................... ..161 11.1.3 block diag ram ........................................................................................................... .....161 11.2 external signal description ............................................................................................... ...........162 11.2.1 scl ? serial clock line ...............................................................................................16 2 11.2.2 sda ? serial da ta line ................................................................................................16 2 11.3 register definition ....................................................................................................... .................162 11.3.1 iic address register (iica) ...........................................................................................16 3 11.3.2 iic frequency divider register (iicf) ..........................................................................163 11.3.3 iic control regist er (iicc1) ..........................................................................................16 6 11.3.4 iic status regist er (iics) .............................................................................................. .166 11.3.5 iic data i/o regi ster (iicd) ..........................................................................................16 7 11.3.6 iic control register 2 (iicc2) .......................................................................................168 11.4 functional description .................................................................................................... ..............169 11.4.1 iic protocol ............................................................................................................ .........169 11.4.2 10-bit address .......................................................................................................... .......172
MC9S08JM16 series data sheet, rev. 2 14 freescale semiconductor 11.4.3 general call address .................................................................................................... ..173 11.5 resets .................................................................................................................... ........................173 11.6 interrupts ................................................................................................................ .......................173 11.6.1 byte transfer interrupt ................................................................................................. ...173 11.6.2 address detect interrupt ................................................................................................ .174 11.6.3 arbitration lost interrupt .............................................................................................. ..174 11.7 initialization/appli cation inform ation .................................................................................... ......175 chapter 12 multi-purpose clock generator (s08mcgv1) 12.1 introducti on .............................................................................................................. .....................177 12.1.1 features ................................................................................................................ ...........179 12.1.2 modes of oper ation ...................................................................................................... ..181 12.2 external signal de scription ............................................................................................... ...........181 12.3 register definition ....................................................................................................... .................182 12.3.1 mcg control register 1 (mcgc1) ...............................................................................182 12.3.2 mcg control register 2 (mcgc2) ...............................................................................183 12.3.3 mcg trim register (mcgtrm) ...................................................................................184 12.3.4 mcg status and control register (mcgsc) .................................................................185 12.3.5 mcg control register 3 (mcgc3) ...............................................................................186 12.4 functional description .................................................................................................... ..............188 12.4.1 operational modes ....................................................................................................... ...188 12.4.2 mode switch ing .......................................................................................................... ....192 12.4.3 bus frequency divider ................................................................................................... 192 12.4.4 low power bit usage ..................................................................................................... 193 12.4.5 internal refere nce clock ................................................................................................ 193 12.4.6 external reference clock ...............................................................................................1 93 12.4.7 fixed frequency clock ................................................................................................... 193 12.5 initialization / appli cation information .................................................................................. ......194 12.5.1 mcg module initialization sequence ............................................................................194 12.5.2 mcg mode swit ching ....................................................................................................19 5 12.5.3 calibrating the internal re ference clock (irc) .............................................................206 chapter 13 real-time counter (s08rtcv1) 13.1 introducti on .............................................................................................................. .....................209 13.1.1 features ................................................................................................................ ...........211 13.1.2 modes of oper ation ...................................................................................................... ..211 13.1.3 block diag ram ........................................................................................................... .....212 13.2 external signal de scription ............................................................................................... ...........212 13.3 register definition ....................................................................................................... .................212 13.3.1 rtc status and control register (rtc sc) ....................................................................213 13.3.2 rtc counter register (rtccnt) ..................................................................................214 13.3.3 rtc modulo register (rtcmod) ................................................................................214 13.4 functional description .................................................................................................... ..............214
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 15 13.4.1 rtc operation ex ample .................................................................................................21 5 13.5 initialization/applicat ion informat ion .................................................................................... ......216 chapter 14 serial communications interface (s08sciv4) 14.1 introducti on .............................................................................................................. .....................219 14.1.1 features ................................................................................................................ ...........221 14.1.2 modes of oper ation ...................................................................................................... ..221 14.1.3 block diag ram ........................................................................................................... .....222 14.2 register definition ....................................................................................................... .................224 14.2.1 sci baud rate registers (s cixbdh, scixbdl) ..........................................................224 14.2.2 sci control register 1 (scixc1) ...................................................................................225 14.2.3 sci control register 2 (scixc2) ...................................................................................226 14.2.4 sci status register 1 (scixs1) ......................................................................................227 14.2.5 sci status register 2 (scixs2) ......................................................................................229 14.2.6 sci control register 3 (scixc3) ...................................................................................230 14.2.7 sci data register (scixd) .............................................................................................23 1 14.3 functional description .................................................................................................... ..............231 14.3.1 baud rate gene ration .......... .......................................................................................... .231 14.3.2 transmitter functiona l descriptio n ................................................................................232 14.3.3 receiver functional description ....................................................................................233 14.3.4 interrupts and stat us flags ............................................................................................. .235 14.3.5 additional sci f unctions ...............................................................................................2 36 chapter 15 16-bit serial peripheral interface (s08spi16v1) 15.1 introducti on .............................................................................................................. .....................239 15.1.1 spi port configuratio n information ...............................................................................239 15.1.2 features ................................................................................................................ ...........242 15.1.3 modes of oper ation ...................................................................................................... ..242 15.1.4 block diagra ms .......................................................................................................... ....242 15.2 external signal de scription ............................................................................................... ...........244 15.2.1 spsck ? spi serial clock ............................................................................................244 15.2.2 mosi ? master data out, slave data in ......................................................................245 15.2.3 miso ? master data i n, slave data out ......................................................................245 15.2.4 ss ? slave select ..........................................................................................................245 15.3 register definition ....................................................................................................... .................245 15.3.1 spi control register 1 (spixc1) ....................................................................................245 15.3.2 spi control register 2 (spixc2) ....................................................................................246 15.3.3 spi baud rate register (spixbr) ..................................................................................248 15.3.4 spi status register (spixs) ............................................................................................2 49 15.3.5 spi data registers ( spixdh:spixdl) ...........................................................................250 15.3.6 spi match registers ( spixmh:spixml) .......................................................................251 15.4 functional description .................................................................................................... ..............252 15.4.1 general ................................................................................................................. ...........252
MC9S08JM16 series data sheet, rev. 2 16 freescale semiconductor 15.4.2 master m ode ............................................................................................................. ......252 15.4.3 slave mode .............................................................................................................. .......253 15.4.4 data transmission length ..............................................................................................25 4 15.4.5 spi clock fo rmats ....................................................................................................... ...255 15.4.6 spi baud rate generation ..............................................................................................25 7 15.4.7 special features ........................................................................................................ ......258 15.4.8 error conditi ons ........................................................................................................ .....259 15.4.9 low power mode options ..............................................................................................260 15.4.10spi interrupts ......................................................................................................... .........261 15.5 initialization/applicat ion informat ion .................................................................................... ......263 15.5.1 spi module initialization example .................................................................................263 chapter 16 timer/pulse-width modulator (s08tpmv2) 16.1 introducti on .............................................................................................................. .....................267 16.1.1 features ................................................................................................................ ...........269 16.1.2 modes of oper ation ...................................................................................................... ..269 16.1.3 block diag ram ........................................................................................................... .....270 16.2 signal desc ription ........................................................................................................ .................272 16.2.1 detailed signal de scriptions ..........................................................................................27 2 16.3 register definition ....................................................................................................... .................276 16.3.1 tpm status and control re gister (tpmxs c) ................................................................276 16.3.2 tpm-counter registers (t pmxcnth:tpmxcntl) ....................................................277 16.3.3 tpm counter modulo registers (tpmxmodh:tpmxmodl) ....................................278 16.3.4 tpm channel n status and control register (tpmxcnsc) ..........................................279 16.3.5 tpm channel value register s (tpmxcnvh:tpmxcnvl) ..........................................281 16.4 functional description .................................................................................................... ..............282 16.4.1 counter ................................................................................................................. ...........283 16.4.2 channel mode se lection ...... ...........................................................................................2 85 16.5 reset overview ............................................................................................................ .................288 16.5.1 general ................................................................................................................. ...........288 16.5.2 description of reset operation .......................................................................................288 16.6 interrupts ................................................................................................................ .......................288 16.6.1 general ................................................................................................................. ...........288 16.6.2 description of interr upt operation .................................................................................289 chapter 17 universal serial bus device controller (s08usbv1) 17.1 introducti on .............................................................................................................. .....................295 17.1.1 clocking require ments ................................................................................................... 295 17.1.2 current consumption in usb suspend ..........................................................................295 17.1.3 3.3 v regulator ......................................................................................................... ......295 17.1.4 features ................................................................................................................ ...........298 17.1.5 modes of oper ation ...................................................................................................... ..298 17.1.6 block diag ram ........................................................................................................... .....299
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 17 17.2 external signal de scription ............................................................................................... ...........300 17.2.1 usbdp ................................................................................................................... .........300 17.2.2 usbdn ................................................................................................................... ........300 17.2.3 v usb33 ......................................................................................................................... .................................... 300 17.3 register definition ....................................................................................................... .................300 17.3.1 usb control register 0 (usbctl0) .............................................................................301 17.3.2 peripheral id regist er (perid) .....................................................................................301 17.3.3 peripheral id complement register (idcomp) ............................................................302 17.3.4 peripheral revision re gister (rev) ...............................................................................302 17.3.5 interrupt status register (intstat) ..............................................................................303 17.3.6 interrupt enable regi ster (intenb) ..............................................................................304 17.3.7 error interrupt status re gister (errstat) ...................................................................305 17.3.8 error interrupt enable re gister (errenb) ...................................................................306 17.3.9 status register (stat) .................................................................................................. ..307 17.3.10control register (ctl) ................................................................................................. ..308 17.3.11address register (addr) ..............................................................................................30 9 17.3.12frame number register (frmnuml, frmnumh) ...................................................309 17.3.13endpoint control register (epctln, n=0-6) .................................................................310 17.4 functional description .................................................................................................... ..............311 17.4.1 block descript ions ...................................................................................................... ....311 17.4.2 buffer descriptor table (bdt) .......................................................................................316 17.4.3 usb transactions ........................................................................................................ ...319 17.4.4 usb packet pr ocessing ................................................................................................... 321 17.4.5 start of frame processing ............................................................................................... 322 17.4.6 suspend/resume .......................................................................................................... ...323 17.4.7 resets .................................................................................................................. ............324 17.4.8 interrupts .............................................................................................................. ...........325 chapter 18 development support 18.1 introducti on .............................................................................................................. .....................327 18.1.1 forcing active background ............................................................................................327 18.1.2 features ................................................................................................................ ...........328 18.2 background debug contro ller (bdc) ......................................................................................... .328 18.2.1 bkgd pin descri ption ...................................................................................................3 29 18.2.2 communication details ..................................................................................................3 30 18.2.3 bdc commands ............................................................................................................ .334 18.2.4 bdc hardware br eakpoint .............................................................................................336 18.3 on-chip debug syst em (dbg) ................................................................................................ ....337 18.3.1 comparators a and b ..................................................................................................... 337 18.3.2 bus capture information and fifo operation ...............................................................337 18.3.3 change-of-flow in formation ..........................................................................................338 18.3.4 tag vs. force breakpoint s and triggers .........................................................................338 18.3.5 trigger modes ........................................................................................................... ......339 18.3.6 hardware breakpoints .................................................................................................... 341
MC9S08JM16 series data sheet, rev. 2 18 freescale semiconductor 18.4 register definition ....................................................................................................... .................341 18.4.1 bdc registers and control bits .....................................................................................341 18.4.2 system background debug force re set register (sbdfr) ..........................................343 18.4.3 dbg registers and c ontrol bits .....................................................................................344 appendix a electrical characteristics a.1 introducti on ................................................................................................................ ....................349 a.2 parameter clas sification.................................................................................................... .............349 a.3 absolute maximum ratings.................................................................................................... .......349 a.4 thermal charac teristic s..................................................................................................... .............350 a.5 esd protection and la tch-up immunity........................................................................................ 351 a.6 dc characteristics.......................................................................................................... ................352 a.7 supply current char acteristics.............................................................................................. .........356 a.8 analog comparator (a cmp) electricals .......................................................................................3 57 a.9 adc characteristics......................................................................................................... ..............357 a.10 external oscillator (x osc) characteristics ................................................................................. .361 a.11 mcg specifi cations ......................................................................................................... ..............362 a.12 ac characteristics......................................................................................................... .................363 a.12.1 control ti ming ........................................................................................................... .....363 a.12.2 timer/pwm (tpm) module timing ...............................................................................364 a.12.3 spi character istics ...................................................................................................... .....365 a.13 flash specifications....................................................................................................... .................369 a.14 usb electricals ............................................................................................................ ..................369 18.5 emc performance ........................................................................................................... ..............370 18.5.1 radiated emis sions ...................................................................................................... ...370 appendix b ordering information an d mechanical drawings b.1 ordering information ........................................................................................................ .............373 b.2 orderable part numbering system ............................................................................................. ...373 b.3 mechanical drawings......................................................................................................... ............373
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 19 chapter 1 device overview 1.1 introduction MC9S08JM16 series mcus are members of the low-cost, high-performance hcs08 family of 8-bit microcontroller units (mcus). all mcus in the fam ily use the enhanced hcs08 core and are available with a variety of modules, memory sizes, memory types, and package types. table 1-1 summarizes the peripheral availability per pa ckage type for the devices available in the MC9S08JM16 series. 1.2 mcu block diagram the block diagram in figure 1-1 shows the structure of the MC9S08JM16 series mcu. table 1-1. devices in the MC9S08JM16 series feature device MC9S08JM16 mc9s08jm8 package 48-pin 44-pin 32- pin 48-pin 44-pin 32-pin flash 16,384 8,192 ram 1024 1024 usb ram 256 256 acmp yes yes a d c8 - c h8 - c h4 - c h8 - c h8 - c h4 - c h iic yes yes irq yes yes k b i775775 sci1 yes yes sci2 yes no yes no spi1 yes yes spi2 yes no yes no tpm1 4-ch 4-ch 2-ch 4-ch 4-ch 2-ch tpm2 2-ch 2-ch usb yes yes i/o pins 37 33 21 37 33 21 package types 48 qfn 44 lqfp 32 lqfp 48 qfn 44 lqfp 32 lqfp
chapter 1 device overview MC9S08JM16 series data sheet, rev. 2 20 freescale semiconductor figure 1-1. MC9S08JM16 series block diagram ptc1/sda ptc0/scl v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta5, pta0 pte0/txd1 pte1/rxd1 ptd1/adp9/acmp? ptd0/adp8/acmp+ ptc5/rxd2 ptc4 ptc3/txd2 ptc2 port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi1) user flash (in bytes) user ram (in bytes) on-chip ice and debug module (dbg) hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pu llup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1). 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. pin contains integrated pullup device. 5. when pin functions as kbi (kbipen = 1) and associated pin is configured to enable the pullup device, kbedgn can be used to reco nfigure the pullup as a pulldown device. 2-channel timer/pwm module (tpm2) ptb5/kbip5/adp5 port b pte5/mosi1 pte4/miso1 pte6/spsck1 pte7/ss1 hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset v ssad v ddad v refh analog-to-digital converter (adc) 4-channel timer/pwm module (tpm1) ptd7 2 ptb4/kbip4/adp4 ptg3/kbip7 ptg2/kbip6 port g 8-channel, 12-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg4/xtal ptg5/extal irq/tpmclk rxd2 txd2 sda scl 6 kbipx kbipx tpmclk spsck1 ss1 miso1 mosi1 tpmclk tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 2 4 usb sie usb endpoint ram full speed usb transceiver usbdp usbdn miso2 ss2 spsck2 mosi2 ptb1/mosi2/adp1 ptb0/miso2/adp0 8-/16-bit real-time counter (rtc) ptb3/ss2 /adp3 ptb2/spsck2/adp2 tpm1chx 3 tpm2ch1 tpm2ch0 2 analog comparator (acmp) system usb 3.3 v voltage regulator v usb33 1024 acmpo acmp+ acmp? ptd2/kbip2/acmpo 8-/16-bit serial peripheral interface module (spi2) mc9s08jm8 = 8,192 MC9S08JM16 = 16,384 v ssosc
chapter 1 device overview MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 21 table 1-2 lists the functional versions of the on-chip modules. 1.3 system clock distribution figure 1-2 shows a simplified clock connection diagram. some modules in the mcu have selectable clock inputs as shown. the clock inputs to the modules indica te the clock(s) that are used to drive the module functions. all memory mapped regi sters associated with the modul es are clocked with busclk. figure 1-2. system clock distribution diagram table 1-2. versions of on-chip modules module version analog comparator (acmp) 2 analog-to-digital converter (adc) 1 central processing unit (cpu) 2 iic module (iic) 2 keyboard interrupt (kbi) 2 multi-purpose clock generator (mcg) 1 real-time counter (rtc) 1 serial communications interface (sci) 4 8-/16-bit serial peripheral interface (spi16) 1 timer pulse-width modulator (tpm) 3 universal serial bus (usb) 1 debug module (dbg) 2 tpm1 tpm2 usb mcg mcgout 2 busclk mcglclk mcgerclk cop 1. the ffclk is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency. 2. adc has min. and max. frequency requirements. see chapter 10, ?analog-to-digital converter (s08adc12v1) ,? and appendix a, ?electrical characteristics ,? for details. 3. flash has frequency requirements for program and erase operation. see appendix a, ?electrical characteristics ,? for details. xosc extal xtal ffclk 1 mcgffclk rtc 1 khz lpo tpmclk mcgirclk 2 iic sci1 sci2 spi1 spi1 bdc cpu usb ram adc 2 ram flash 3 lpo clock
chapter 1 device overview MC9S08JM16 series data sheet, rev. 2 22 freescale semiconductor the mcg supplies the following clock sources: ? mcgout ? this clock source is used as th e cpu, usb ram and usb module clock, and is divided by two to generate the peripheral bus clock (busclk). control bits in the mcg control registers determine which of the three clock sources is connected: ? internal reference clock ? external reference clock ? frequency-locked loop (fll) or phase-locked loop (pll) output see chapter 12, ?multi-purpose clock generator (s08mcgv1) ,? for details on configuring the mcgout clock. ? mcglclk ? this clock source is derived from the digitally cont rolled oscillator (dco) of the mcg. development tools can select this in ternal self-clocked source to speed up bdc communications in systems wh ere the bus clock is slow. ? mcgirclk ? this is the internal reference cloc k and can be selected as the real-time counter (rtc) clock source. chapter 12, ?multi-purpose cl ock generator (s08mcgv1) , ? explains the mcgirclk in more detail. see chapter 13, ?real-time counter (s08rtcv1) ,? for more information regarding the use of mcgirclk. ? mcgerclk ? this is the external reference cloc k and can be selected as the clock source of rtc and adc module. section 12.4.6, ?external reference clock ,? explains the mcgerclk in more detail. see chapter 13, ?real-time counter (s08rtcv1) ,? and chapter 10, ?analog-to-digital converter (s08adc12v1) ,? for more informati on regarding the use of mcgerclk with these modules. ? mcgffclk ? this clock source is divided by two to generate ffclk after being synchronized to the busclk. it can be selected as clock s ource for the tpm modules. the frequency of the mcgffclk is determined by the settings of the mcg. see the section 12.4.7, ?fixed frequency clock,? for details. ? lpo clock? this clock is generated from an inte rnal low power oscillator that is completely independent of the mcg module. the lpo clock can be selected as the clock source to the rtc or cop modules. see chapter 13, ?real-time counter (s08rtcv1) ,? and section 5.4, ?computer operating properly (cop) watchdog ,? for details on using the lpo clock with these modules. ? tpmclk ? tpmclk is the optiona l external clock source for the tpm modules. the tpmclk must be limited to 1/4th the frequency of the busclk for synchronization. see chapter 16, ?timer/pulse-width modulator (s08tpmv2) ,? for more details.
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 23 chapter 2 pins and connections 2.1 introduction this chapter describes signals that connect to packag e pins. it includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 device pin assignment figure 2-1 shows the 48-pin qfn pin assi gnments for the MC9S08JM16. see table 2-1 for pin availability by package pin count. figure 2-1. MC9S08JM16 series in 48-pin qfn package ptf4/tpm2ch0 1 2 3 4 5 6 7 8 reset ptf0/tpm1ch2 v usb33 usbdp usbdn v ss v dd pte7/ss1 pte6/spsck1 ptb4/kbip4/adp4 ptb5/kbip5/adp5 ptd0/adp8/acmp+ ptd1/adp9/acmp? ptb1/mosi2/adp1 ptg2/kbip6 ptc5/rxd2 ptg4/xtal bkgd/ms ptg3/kbip7 ptd2/kbip2/acmpo 31 30 29 28 27 26 14 15 16 17 18 19 37 3839 13 24 25 36 48 9 ptf5/tpm2ch1 10 ptf6 11 pte0/txd1 12 pte3/tpm1ch1 ptg0/kbip0 20 ptg1/kbip1 21 pta0 22 23 ptb3/ss2 /adp3 ptb2/spsck2/adp2 ptg5/extal 40 v ssosc 41 ptc0/scl 42 ptc1/sda 43 ptf1/tpm1ch3 pte1/rxd1 pte2/tpm1ch0 v ddad /v refh 32 33 34 v ssad /v refl 35 ptc3/txd2 47 46 45 ptc2 44 ptc4 irq/tpmclk pte4/miso1 pte5/mosi1 ptb0/miso2/adp0 pta5 ptd7 48-pin qfn
chapter 2 pins and connections MC9S08JM16 series data sheet, rev. 2 24 freescale semiconductor figure 2-2 shows the 44-pin lqfp pi n assignments for the mc 9s08jm16 devices. see table 2-1 for pin availability by package pin count. figure 2-2. MC9S08JM16 series in 44-pin lqfp package figure 2-3 shows the 32-pin lqfp pi n assignments for the mc 9s08jm16 devices. see table 2-1 for pin availability by package pin count. ptf4/tpm2ch0 1 2 3 4 5 6 7 8 reset ptf0/tpm1ch2 v usb33 usbdp usbdn v ss v dd pte7/ss1 pte6/spsck1 ptb4/kbip4/adp4 ptb5/kbip5/adp5 ptd0/adp8/acmp+ ptd1/adp9/acmp? ptb1/mosi2/adp1 ptg2/kbip6 ptc5/rxd2 ptg4/xtal bkgd/ms ptg3/kbip7 ptd2/kbip2/acmpo 31 30 29 28 27 26 13 14 15 16 17 18 34 35 12 22 23 33 44 9 ptf5/tpm2ch1 10 pte0/txd1 11 pte3/tpm1ch1 ptg0/kbip0 19 ptg1/kbip1 20 21 ptb3/ss2 /adp3 ptb2/spsck2/adp2 ptg5/extal 36 v ssosc 37 ptc0/scl 38 ptc1/sda 39 ptf1/tpm1ch3 pte1/rxd1 pte2/tpm1ch0 v ddad /v refh 32 v ssad /v refl ptc3/txd2 43 42 41 ptc2 40 ptc4 irq/tpmclk pte4/miso1 pte5/mosi1 ptb0/miso2/adp0 44-pin lqfp 25 24
chapter 2 pins and connections MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 25 figure 2-3. MC9S08JM16 series in 32-pin lqfp package 2.3 recommended system connections figure 2-4 shows pin connections that are common to almost all MC9S08JM16 series application systems. ptf4/tpm2ch0 1 2 3 4 5 6 7 8 reset usbpdp usbdn v ss v dd pte7/ss1 pte6/spsck1 ptd1/adp9/acmp? v ddad /v refh ptb4/kbip4/adp4 ptg2/kbip6 ptg4/xtal bkgd/ms ptg3/kbip7 22 21 20 19 18 17 10 11 12 13 14 15 9 24 32 ptf5/tpm2ch1 pte0/txd1 pte3/tpm1ch1 16 ptd0/adp8/acmp+ ptb5/kbip5/adp5 ptg5/extal v ssosc 25 ptc0/scl 26 ptc1/sda 27 pte1/rxd1 pte2/tpm1ch0 v ssad /v refl 23 ptd2/kbip2/acmpo 31 30 29 28 irq/tpmclk pte4/miso1 pte5/mosi1 v usb33 32-pin lqfp
chapter 2 pins and connections MC9S08JM16 series data sheet, rev. 2 26 freescale semiconductor figure 2-4. basic system connections MC9S08JM16 v dd v ss reset optional manual reset port a v dd 1 background header c by 0.1 f c blk 10 f + 5 v + system power i/o and peripheral interface to system application pta0, pta5 v dd port b ptb0/miso2/adp0 ptb1/mosi2/adp1 ptb2/spsck2/adp2 ptb3/ss2 /adp3 ptb4/kbip4/adp4 ptb5/kbip5/adp5 port c ptc0/scl ptc1/sda ptc2 ptc3/txd2 ptc4 ptc5/rxd2 port d ptd0/adp8/acmp+ ptd1/adp9/acmp? ptd7 pte0/txd1 pte1/rxd1 pte2/tpm1ch0 pte3/tpm1ch1 pte4/miso1 pte5/mosi1 pte6/spsck1 pte7/ss1 ptg0/kbip0 ptg1/kbip1 ptg2/kbip6 ptg3/kbip7 ptf0/tpm1ch2 ptf1/tpm1ch3 ptf4/tpm2ch0 ptf5/tpm2ch1 ptf6 irq irq/tpmclk notes: 1. external crystal ci rcuity is not required if using the mcg internal clock option. for usb operation, an external crystal is r equired. 2. xtal and extal are the same pins as ptg4 and ptg5, respectively. 3. rc filters on reset and irq are recommended for emc-sensitive applications. 4. r pudp is shown for full-speed usb only. the diagram show s a configuration where the on-chip regulator and r pudp are enabled. the voltage regulator output is used for r pudp. r pudp can optionally be disabled if using an external pullup resistor on usbdp 5. v bus is a 5.0 v supply from upstream port that can be used for usb operation. 6. usbdp and usbdn are powered by the 3.3 v regulator. v ddad v ssad c byad 0.1 f v refl v refh ptg4/xtal ptg5/extal v dd 4.7 k ? 0.1 f v dd 4.7 k ?10 k 0.1 f 10 k 2 43 usbdn v usb33 usbdp v bus port e port f port g usb series-b connector v usb33 3.3-v reference r pudp ptd2/kbip2/acmpo bkgd/ms xtal extal c2 c1 x1 r f r s note 1 v ssosc 0.47 f + 4.7 f
chapter 2 pins and connections MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 27 2.3.1 power (v dd , v ss , v ssosc , v ddad , v ssad , v usb33 ) v dd and v ss are the primary power supply pi ns for the mcu. this voltage source supplies power to all i/o buffer circuitry and to an internal voltage regulator. the intern al voltage regulator provides regulated lower-voltage source to the cpu and ot her internal circuitry of the mcu. typically, application systems have tw o separate capacitors across the power pins. in this case, there is a bulk electrolytic capac itor, such as a 10 f tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1 f ceramic bypass capacitor located as near as prac tical to the paired v dd and v ss power pins to suppress high-frequenc y noise. the MC9S08JM16 has a v ssosc pin. this pin must be connected to the system ground plane or to the primary v ss pin through a low-im pedance connection. v ddad and v ssad are the analog power supply pi ns for the mcu. this volta ge source supplies power to the adc module. a 0.1 f ceramic bypass capacitor must be located as near to the anal og power pins as practical to suppress high-frequency noise. v usb33 is connected to the internal usb 3.3 v regulator. v usb33 maintains an output voltage of 3.3 v and only can source enough current fo r internal usb transceiver and usb pullup resistor. two separate capacitors (4.7 f bulk electrolytic stability cap acitor and 0.47 f ceramic bypass capacitors) must be connected across this pin to ground to decrease the output ripple of this voltage regulator when it is enabled. 2.3.2 oscillator (xtal, extal) immediately after reset, th e mcu uses an internally generated cl ock provided by the multi-purpose clock generator (mcg) module. for more information on the mcg, see chapter 12, ?multi-purpose clock generator (s08mcgv1) .? the oscillator (xosc) in this mcu is a pierce os cillator that can accommodate a crystal or ceramic resonator. rather than a crystal or ceramic resonator, an external osci llator can be connected to the extal input pin. r s (when used) and r f must be low-inductance resistors such as carbon composition resistors. wire-wound resistors, and some metal film resistors, have too much i nductance. c1 and c2 normally must be high-quality ceramic capacitors that are specifically designed for high-frequency applications. r f is used to provide a bias path to keep the extal in put in its linear range duri ng crystal startup; its value is not generally critical . typical systems use 1 m to 10 m . higher values are sens itive to humidity and lower values reduce gain and (in ex treme cases) could prevent startup. c1 and c2 are typically in the 5 pf to 25 pf range and are chosen to match the requirements of a specific crystal or resonator. be sure to take into acc ount printed circuit board (p cb) capacitance and mcu pin capacitance when selecting c1 and c2. the crystal manufacturer typically speci fies a load capacitance which is the series combination of c1 and c2 (w hich are usually the same size). as a first-order approximation, use 10 pf as an estimate of combined pin and pcb capacitance for each oscillator pin (extal and xtal).
chapter 2 pins and connections MC9S08JM16 series data sheet, rev. 2 28 freescale semiconductor 2.3.3 reset pin reset is a dedicated pin with a built-i n pullup device. it has input hystere sis, a high current output driver, and no output slew rate control. internal power-on reset a nd low-voltage reset circ uitry typically make external reset circuitry unnecessary . this pin is normally connected to the standard 6-pin background debug connector, so a development system can direct ly reset the mcu system. if desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). whenever any reset is initiated (whe ther from an external source or from an internal source, the reset pin is driven low for approximately 66 bus cycles a nd released. the reset circuity decodes the cause of reset and records it by setting a corresponding bit in the system control reset status register (srs). in emc-sensitive applications, an external rc filter is recommended on the reset pin. see figure 2-4 for an example. 2.3.4 background/mode select (bkgd/ms) when in reset, the bkgd/ms pin functions as a mode select pin. immediately af ter reset rises, the pin functions as the background pin and can be used for background debug communication. while function- ing as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, a stan- dard output driver, and no out put slew rate control. if nothing is connected to this pi n, the mcu will enter normal operating m ode at the rising edge of reset. if a debug system is connected to the 6-pin standard background de bug header, it can hold bkgd/ms low during the rising edge of reset which fo rces the mcu to active background mode. the bkgd pin is used primarily for background debug controller (bdc) communi cations using a custom protocol that uses 16 clock cycles of the target mcu?s bdc clock per bit time. the target mcu?s bdc clock could be as fast as the bus clock rate, so there must never be any significant capacitance connected to the bkgd/ms pin that could interfer e with background serial communications. although the bkgd pin is a ps eudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. small capacitances from cables and the absolute valu e of the internal pullup devi ce play almost no role in determining rise and fall times on the bkgd pin. 2.3.5 adc reference pins (v refh , v refl ) the v refh and v refl pins are the voltage reference high and voltage reference low inputs respectively for the adc module. 2.3.6 external interrupt pin (irq) the irq pin is the input source for the irq interrupt a nd is also the input for th e bih and bil instructions. if the irq function is not enabled, this pin can be used for tpmclk. in emc-sensitive applications, an external rc filter is recommended on the irq pin. see figure 2-4 for an example.
chapter 2 pins and connections MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 29 2.3.7 usb data pins (usbdp, usbdn) the usbdp (d+) and usbdn (d?) pi ns are the analog input/output line s to/from full-speed internal usb transceiver. an optional internal pullup resistor for the usbdp pin, r pudp , is available. 2.3.8 general-purpose i/o and peripheral ports the MC9S08JM16 series of mcus support up to 37 ge neral-purpose i/o pins, which are shared with on-chip peripheral functions (timers, serial i/o, adc, keyboard interrupts, etc.). when a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and en able or disable slew rate control. when a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pullup device. for information about controlling these pi ns as general-purpose i/o pins, see the chapter 6, ?parallel input/output .? for information about how and when on-chip peripheral syst ems use these pins, see the appropriate module chapter. immediately after reset, all pins ar e configured as high-impedance general-purpose inputs with internal pullup devices disabled. note when an alternative function is first en abled, it is possible to get a spurious edge to the module, user software must clear out any associ ated flags before interrupts are enabled. table 2-1 illustrates the priority if multiple modules are enabled. the highest priority m odule will have control over the pin. selecting a higher priority pin function with a lower priority function already enabled can cause spurious e dges to the lower priority module. disable all modules that share a pin before enabli ng another module.
chapter 2 pins and connections MC9S08JM16 series data sheet, rev. 2 30 freescale semiconductor pin number lowest <--priority--> highest 48 44 32 port pin alt1 alt2 11?ptc4 221 irq tpmclk 3 3 2 reset 4 4 ? ptf0 tpm1ch2 5 5 ? ptf1 tpm1ch3 663ptf4 tpm2ch0 774ptf5 tpm2ch1 8??ptf6 9 8 5 pte0 txd1 10 9 6 pte1 rxd1 11 10 7 pte2 tpm1ch0 12 11 8 pte3 tpm1ch1 13 12 9 pte4 miso1 14 13 10 pte5 mosi1 15 14 11 pte6 spsck1 16 15 12 pte7 ss1 17 16 13 v dd 18 17 14 v ss 19 18 15 usbdn 20 19 16 usbdp 21 20 17 v usb33 22 21 ? ptg0 kbip0 23 22 ? ptg1 kbip1 24 ? ? pta0 25 ? ? pta5 26 23 ? ptb0 miso2 adp0 27 24 ? ptb1 mosi2 adp1 28 25 ? ptb2 spsck2 adp2 29 26 ? ptb3 ss2 adp3 30 27 18 ptb4 kbip4 adp4 31 28 19 ptb5 kbip5 adp5 32 29 20 ptd0 adp8 acmp+ 33 30 21 ptd1 adp9 acmp? 34 31 22 v ddad v refh 35 32 23 v refl v ssad 36 33 24 ptd2 kbip2 acmpo 37 ? ? ptd7 38 34 25 ptg2 kbip6 39 35 26 ptg3 kbip7 40 36 27 bkgd ms 41 37 28 ptg4 xtal 42 38 29 ptg5 extal 43 39 30 v ssosc 44 40 31 ptc0 scl 45 41 32 ptc1 sda 46 42 ? ptc2 47 43 ? ptc3 txd2 48 44 ? ptc5 rxd2 pin number lowest <--priority--> highest 48 44 32 port pin alt1 alt2 table 2-1. pin availability by package pin-count
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 31 chapter 3 modes of operation 3.1 introduction the operating modes of the MC9S08JM16 series are described in this chap ter. entry into each mode, exit from each mode, and functionality wh ile in each mode are described. 3.2 features ? active background mode for code development ? wait mode: ? cpu halts operation to conserve power ? system clocks continue to run ? full voltage regulation is maintained ? stop modes: cpu and bus clocks stopped ? stop2: partial power down of internal ci rcuits; ram and usb ra m contents retained ? stop3: all internal circuits pow ered for fast recove ry; ram, usb ram, and register contents are retained 3.3 run mode run is the normal operating mode for the mc9s08 jm16 series. this mode is selected upon the mcu exiting reset if the bkgd/ms pin is hi gh. in this mode, the cpu executes code from internal memory with execution beginning at the address fetched from memory at 0xfffe:0xffff after reset. 3.4 active background mode the active background mode functions are manage d through the background de bug controller (bdc) in the hcs08 core. the bdc, together with the on-chip in-circuit emulator (ice) debug module (dbg), provides the means for analyzing mcu operation during software development. active background mode is entered in any of five ways: ? when the bkgd/ms pin is low during por or immediately after issuing a background debug force reset (see section 5.7.3, ?system background debug force reset register (sbdfr) ?) ? when a background command is received through the bkgd pin ? when a bgnd instruction is executed ? when encountering a bdc breakpoint ? when encountering a dbg breakpoint
chapter 3 modes of operation MC9S08JM16 series data sheet, rev. 2 32 freescale semiconductor after entering active background mode, the cpu is held in a suspended state waiting for serial background commands rather than executing instructi ons from the user application program. background commands are of two types: ? non-intrusive commands, defined as commands that can be issu ed while the user program is running. non-intrusive commands can be issued through the bkgd pin while the mcu is in run mode; non-intrusive commands ca n also be executed when the mcu is in the active background mode. non-intrusive commands include: ? memory access commands ? memory-access-with-status commands ? bdc register access commands ? the background command ? active background commands, which can only be executed while the mcu is in active background mode. active background commands include commands to: ? read or write cpu registers ? trace one user program instruction at a time ? leave active background mode to return to the user application program (go) the active background mode is used to program a bootloader or user a pplication program into the flash program memory before the mcu is operated in r un mode for the first time. when the MC9S08JM16 series are shipped from the freesca le factory, the flash program memory is erased by default unless specifically noted, so there is no program that could be executed in run mode until the flash memory is initially programmed. the active background mode can also be used to erase and reprogram the flash memory after it has been previously programmed. for additional information about the active background mode, refer to the chapter 18, ?development support .? 3.5 wait mode wait mode is entered by executing a wait instruct ion upon execution of the wa it instruction. the cpu enters a low-power state in which it is not clocked. the i bit in the condi tion code register (ccr) is cleared when the cpu enters wait mode, en abling interrupts. when an interrupt request occurs, the cpu exits wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. while the mcu is in wait mode, ba ckground debug commands can be used on the fo llowing restrictions. ? only the background command and memory-ac cess-with-status commands are available while the mcu is in wait mode. ? the memory-access-with-status commands do not al low memory access, but they report an error indicating that the mcu is in stop or wait mode. ? the background command can be used to wake the mcu from wait mode and enter active background mode.
chapter 3 modes of operation MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 33 3.6 stop modes one of two stop modes is entered upon execution of a stop instructi on when stope in so pt1 is set. in any stop mode, the bus and cpu cl ocks are halted. the mcg module can be configured to leave the reference clocks running. see chapter 12, ?multi-purpose cl ock generator (s08mcgv1) ,? for more information. hcs08 devises that are designe d for low-voltage operation (1.8 to 3.6 v) support stop1 mode. the MC9S08JM16 series of mcus do not support stop1 mode. table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions. the selected mode is entered fo llowing the execution of a stop instruction. 3.6.1 stop3 mode stop3 mode is entered by executing a stop in struction under the conditions shown in table 3-1 . the states of all of the internal re gisters and logic, ram contents, a nd i/o pin states are maintained. stop3 can be exited by asserting reset , or by an interrupt from one of the following sources: the real-time clock (rtc) interrupt, the usb resume interrupt, lvd, adc, irq, kbi, sci or the acmp. if stop3 is exited by means of the reset pin, then the mcu is reset and operation will resume after taking the reset vector. exit by means of one of the internal interrupt sources results in the mcu taking the appropriate interrupt vector. 3.6.1.1 lvd enabled in stop mode the lvd system is capable of genera ting either an interrupt or a reset when the supply voltage drops below the lvd voltage. if the lvd is enable d in stop (lvde and lvds e bits in spmsc1 both set) at the time the cpu executes a stop instruction, then the voltage regulator remains activ e during stop mode. if the user attempts to enter stop2 with the lvd enabled for stop, the mcu will enter stop3 instead. for the adc to operate the lvd must be left enabled when entering stop3. table 3-1. stop mode selection stope enbdm 1 1 enbdm is located in the bdcscr which is only accessible through bdc commands, see section 18.4.1.1, ?bdc status and control register (bdcscr) .? lv d e lv d s e p p d c s t o p m o d e 0 x x x stop modes disabled; illegal opcode reset if stop instruction executed 1 1 x x stop3 with bdm enabled 2 2 when in stop3 mode with bdm enabled, the s idd will be near r idd levels because internal clocks are enabled. 1 0 both bits must be 1 x stop3 with voltage regulator active 1 0 either bit a 0 0 stop3 1 0 either bit a 0 1 stop2
chapter 3 modes of operation MC9S08JM16 series data sheet, rev. 2 34 freescale semiconductor for the acmp to operate when acgb s in acmpsc is set, the lvd must be left enabled when entering stop3. for the xosc to operate with an external reference when range in mcgc2 is set, the lvd must be left enabled when entering stop3. 3.6.1.2 active bdm enabled in stop mode entry into the active bac kground mode from run mode is enabled if enbdm in bdcscr is set. this register is described in chapter 18, ?development support .? if enbdm is set when the cpu executes a stop instruction, the system clocks to the bac kground debug logic remain active when the mcu enters stop mode. because of this, bac kground debug communication remains possible. in addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. if the user attempts to enter stop2 with enbdm set, the mcu will enter stop3 instead. most background commands are not available in stop mode. the memo ry-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from stop and enter active background mode if the enbdm bit is set. af ter entering background de bug mode, all background commands are available. 3.6.2 stop2 mode stop2 mode is entered by executing a stop in struction under the c onditions as shown in table 3-1 . most of the internal circuitry of the mc u is powered off in stop2, with the exception of the ram. upon entering stop2, all i/o pin control signals are latched so that the pins retain their states during stop2. exit from stop2 is performed by a sserting either wake-up pin: reset or irq. note irq/tpmclk always func tions as an active-low wakeup input when the mcu is in stop2, regardless of how th e pin is configured before entering stop2. the pullup on this pin is always disabled in stop2. this pin must be driven or pulled high externally while in stop2 mode. in addition, the rtc interrupt can wa ke the mcu from stop2, if enabled. upon wake-up from stop2 mode, the mcu starts up as from a power-on reset (por): ? all module control and status registers are reset ? the lvd reset function is enabled and th e mcu remains in th e reset state if v dd is below the lvd trip point (low trip poi nt selected due to por) ? the cpu takes the reset vector in addition to the above, upon waking up from stop2, the ppd f bit in spmsc2 is set. this flag is used to direct user code to go to a stop2 recovery routine. ppdf remains set and the i/o pin states remain latched until a 1 is written to ppdack in spmsc2.
chapter 3 modes of operation MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 35 to maintain i/o states for pins configured as general-purpose i/o before entering stop2, the user must restore the contents of the i/o port re gisters, which have been saved in ram, to the port registers before writing to the ppdack bit. if the port registers are not restored from ram before writing to ppdack, then the pins will switch to their reset states when ppdack is written. for pins that were configured as peripheral i/o, the user must reconfigure the peripheral module that interfaces to the pin before writing to the ppdack bit. if the peripheral module is not enabled before writing to ppdack, the pins will be controlled by their associated port control registers when the i/o latches are opened. 3.6.3 on-chip peripheral modules in stop modes when the mcu enters any stop mode, system clocks to the internal periphera l modules are stopped. even in the exception case (enbdm = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halte d to reduce power consumption. refer to section 3.6.2, ?stop2 mode ,? and section 3.6.1, ?stop3 mode ,? for specific information on sy stem behavior in stop modes. table 3-2. stop mode behavior peripheral mode stop2 stop3 cpu off standby ram standby standby flash off standby parallel port registers off standby adc off optionally on 1 1 requires the asynchronous adc clock and lvd to be enabled, else in standby. acmp off optionally on 2 2 if acgbs in acmpsc is set, lvd must be enabled, else in standby. mcg off optionally on 3 3 irclken and irefsten set in mcgc1, else in standby. iic off standby rtc optionally on 4 4 rtcps[3:0] in rtcsc does not equal to 0 before entering stop, else off. optionally on 4 sci off standby spi off standby tpm off standby system voltage regulator off standby xosc off optionally on 5 i/o pins states held states held usb (sie and transceiver) off optionally on 6 usb 3.3 v regulator off standby usb ram standby standby
chapter 3 modes of operation MC9S08JM16 series data sheet, rev. 2 36 freescale semiconductor 5 erclken and erefsten set in mcgc2, else in standby. for high frequency range (range in mcgc2 set), it also requires the lvd to be enabled in stop3. 6 usben in ctl is set and usbphyen in usbctl0 is set, else off.
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 37 chapter 4 memory 4.1 MC9S08JM16 series memory map figure 4-1 shows the memory map for the MC9S08JM16 series. on-chip memory in the MC9S08JM16 series of mcus consists of ra m, flash program memory for nonvolat ile data storage, plus i/o and control/status registers. the regi sters are divided into three groups: ? direct-page registers (0x0000 through 0x00af) ? high-page registers (0x1800 through 0x185f) ? nonvolatile registers (0xffb0 through 0xffbf)
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 38 freescale semiconductor MC9S08JM16 mc9s08jm8 0x0000 direct page registers 0x0000 direct page registers 0x00af 0x00af 0x00b0 ram 1,024 bytes 0x00b0 ram 1,024 bytes 0x04af 0x04af 0x04b0 unimplemented 0x04b0 unimplemented 0x08af 0x08af 0x08b0 unimplemented 0x08b0 unimplemented 0x17ff 0x17ff 0x1800 high page registers 0x1800 high page registers 0x185f 0x185f 0x1860 usb ram ? 256 bytes 0x1860 usb ram ? 256 bytes 0x195f 0x195f 0x1960 unimplemented 0x1960 unimplemented 0xbfff 0xc000 flash 16,384 bytes 0xdfff 0xe000 flash 8,192 bytes 0xffff 0xffff figure 4-1. MC9S08JM16 series memory map
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 39 4.1.1 reset and interrupt vector assignments figure 4-1 shows address assignments for re set and interrupt vector s. the vector names shown in this table are the labels used in the freescale-provided equate file for the mc 9s08jm16 series. for more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to chapter 5, ?resets, interrupts, and system configuration .? table 4-1. reset and interrupt vectors address (high/low) vector vector name 0xffc0:ffc1 to 0xffc2:ffc3 unused vector space 0xffc4:ffc5 rtc vrtc 0xffc6:ffc7 iic viic 0xffc8:ffc9 acmp vacmp 0xffca:ffcb adc conversion vadc 0xffcc:ffcd kbi vkeyboard 0xffce:ffcf sci2 transmit vsci2tx 0xffd0:ffd1 sci2 receive vsci2rx 0xffd2:ffd3 sci2 error vsci2err 0xffd4:ffd5 sci1 transmit vsci1tx 0xffd6:ffd7 sci1 receive vsci1rx 0xffd8:ffd9 sci1 error vsci1err 0xffda:ffdb tpm2 overflow vtpm2ovf 0xffdc:ffdd tpm2 channel 1 vtpm2ch1 0xffde:ffdf tpm2 channel 0 vtpm2ch0 0xffe0:ffe1 tpm1 overflow vtpm1ovf 0xffe2:ffe3 reserved reserved 0xffe4:ffe5 reserved reserved 0xffe6:ffe7 tpm1 channel 3 vtpm1ch3 0xffe8:ffe9 tpm1 channel 2 vtpm1ch2 0xffea:ffeb tpm1 channel 1 vtpm1ch1 0xffec:ffed tpm1 channel 0 vtpm1ch0 0xffee:ffef reserved reserved 0xfff0:fff1 usb status vusb 0xfff2:fff3 spi2 vspi2 0xfff4:fff5 spi1 vspi1
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 40 freescale semiconductor 4.2 register addresses and bit assignments the registers in the MC9S08JM16 series are divided into these three groups: ? direct-page registers are located in the first 176 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. ? high-page registers are used much less ofte n, so they are located above 0x1800 in the memory map. this leaves more room in the direct page for more frequently used registers and variables. ? the nonvolatile register area consists of a block of 16 locations in flash memory at 0xffb0?0xffbf. nonvolatile register locations include: ? three values which are loaded in to working registers at reset ? an 8-byte backdoor comparison key which optionall y allows a user to gain controlled access to secure memory because the nonvolatile register locations are flash memory, they must be erased and programmed like other flash memory locations. direct-page registers can be accessed with efficient direct addressing mode inst ructions. bit manipulation instructions can be used to access any bit in any direct-page register. table 4-2 is a summary of all user-accessible direct-page re gisters and control bits. the direct-page registers in table 4-2 can use more efficient direct addressing mode, which requires only the lower byte of the address. becaus e of this, the lower byte of the addre ss in column one is shown in bold text. in table 4-3 and table 4-4 , the whole address in column one is shown in bold. in table 4-2 , table 4-3 , and table 4-4 , the register names in column two are shown in bold to set them apart from the bit names to the right. cells that are not associated with named bi ts are shaded. a shaded cell with a 0 indicates this unused bit always reads as a 0. shaded cells with dashes indicat e unused or reserved b it locations that could read as 1s or 0s. 0xfff6:fff7 mcg loss of lock vlol 0xfff8:fff9 low voltage detect vlvd 0xfffa:fffb irq virq 0xfffc:fffd swi vswi 0xfffe:ffff reset vreset table 4-1. reset and interrupt vectors (continued) address (high/low) vector vector name
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 41 table 4-2. direct-page register summary (sheet 1 of 4) address register name b i t 7654321b i t 0 0x00 00 ptad ? ?ptad5 ? ? ? ?ptad0 0x00 01 ptadd ? ?ptadd5 ? ? ? ?ptadd0 0x00 02 ptbd ? ? ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 0x00 03 ptbdd ? ? ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 0x00 04 ptcd ? ? ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 0x00 05 ptcdd ? ? ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 0x00 06 ptdd ptdd7 ? ? ? ? ptdd2 ptdd1 ptdd0 0x00 07 ptddd ptddd7 ? ? ? ? ptddd2 ptddd1 ptddd0 0x00 08 pted pted7 pted6 pted5 pted4 pted3 pted2 pted1 pted0 0x00 09 ptedd ptedd7 ptedd6 ptedd5 ptedd4 ptedd3 ptedd2 ptedd1 ptedd0 0x00 0a ptfd ? ptfd6 ptfd5 ptfd4 ? ? ptfd1 ptfd0 0x00 0b ptfdd ? ptfdd6 ptfdd5 ptfdd4 ? ? ptfdd1 ptfdd0 0x00 0c ptgd ? ? ptgd5 ptgd4 ptgd3 ptgd2 ptgd1 ptgd0 0x00 0d ptgdd ? ? ptgdd5 ptgdd4 ptgdd3 ptgdd2 ptgdd1 ptgdd0 0x00 0e acmpsc acme acbgs acf acie aco acope acmod 0x00 0f reserved ? ? ? ? ? ? ? ? 0x00 10 adcsc1 coco aien adco adch 0x00 11 adcsc2 adact adtrg acfe acfgt 0 0 r r 0x00 12 adcrh 0 0 0 0 adr11 adr10 adr9 adr8 0x00 13 adcrl adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0x00 14 adccvh 0 0 0 0 adcv11 adcv10 adcv9 adcv8 0x00 15 adccvl adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 0x00 16 adccfg adlpc adiv adlsmp mode adiclk 0x00 17 apctl1 ? ? adpc5 adpc4 adpc3 adpc2 adpc1 adpc0 0x00 18 apctl2 ? ? ? ? ? ? adpc9 adpc8 0x00 19 ? 0x00 1a reserved ? ? ? ? ? ? ? ? 0x00 1b irqsc 0 irqpdd irqedg irqpe irqf irqack irqie irqmod 0x00 1c kbisc 0 0 0 0 kbf kback kbie kbmod 0x00 1d kbipe kbipe7 kbipe6 kbipe5 kbipe4 0 kbipe2 kbipe1 kbipe0 0x00 1e kbies kbedg7 kbedg6 kbedg5 kbedg4 0 kbedg2 kbedg1 kbedg0 0x00 1f reserved ? ? ? ? ? ? ? ? 0x00 20 tpm1sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 21 tpm1cnth bit 15 14 13 12 11 10 9 bit 8 0x00 22 tpm1cntl bit 7654321bit 0 0x00 23 tpm1modh bit 15 14 13 12 11 10 9 bit 8 0x00 24 tpm1modl bit 7654321bit 0 0x00 25 tpm1c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 26 tpm1c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 27 tpm1c0vl b i t 7654321b i t 0 0x00 28 tpm1c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 29 tpm1c1vh bit 15 14 13 12 11 10 9 bit 8
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 42 freescale semiconductor 0x00 2a tpm1c1vl b i t 7654321b i t 0 0x00 2b tpm1c2sc ch2f ch2ie ms2b ms2a els2b els2a 0 0 0x00 2c tpm1c2vh bit 15 14 13 12 11 10 9 bit 8 0x00 2d tpm1c2vl b i t 7654321b i t 0 0x00 2e tpm1c3sc ch3f ch3ie ms3b ms3a els3b els3a 0 0 0x00 2f tpm1c3vh bit 15 14 13 12 11 10 9 bit 8 0x00 30 tpm1c3vl b i t 7654321b i t 0 0x00 31 ? 0x00 37 reserved ? ? ? ? ? ? ? ? 0x00 38 sci1bdh lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 0x00 39 sci1bdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 0x00 3a sci1c1 loops sciswai rsrc m wake ilt pe pt 0x00 3b sci1c2 tie tcie rie ilie te re rwu sbk 0x00 3c sci1s1 tdre tc rdrf idle or nf fe pf 0x00 3d sci1s2 lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf 0x00 3e sci1c3 r8 t8 txdir txinv orie neie feie peie 0x00 3f sci1d b i t 7654321b i t 0 0x00 40 sci2bdh lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 0x00 41 sci2bdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 0x00 42 sci2c1 loops sciswai rsrc m wake ilt pe pt 0x00 43 sci2c2 tie tcie rie ilie te re rwu sbk 0x00 44 sci2s1 tdre tc rdrf idle or nf fe pf 0x00 45 sci2s2 lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf 0x00 46 sci2c3 r8 t8 txdir txinv orie neie feie peie 0x00 47 sci2d b i t 7654321b i t 0 0x00 48 mcgc1 clks rdiv irefs irclken irefsten 0x00 49 mcgc2 bdiv range hgo lp erefs erclken erefsten 0x00 4a mcgtrm trim 0x00 4b mcgsc lols lock pllst irefst clkst oscinit ftrim 0x00 4c mcgc3 lolie plls cme 0v d i v 0x00 4d mcgt 0 0 0 0 0 0 0 0 0x00 4e ? 0x00 4f reserved ? ? ? ? ? ? ? ? 0x00 50 spi1c1 spie spe sptie mstr cpol cpha ssoe lsbfe 0x00 51 spi1c2 spmie spimode 0 modfen bidiroe 0 spiswai spc0 0x00 52 spi1br 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 0x00 53 spi1s sprf spmf sptef modf 0 0 0 0 0x00 54 spi1dh bit 15 14 13 12 11 10 9 bit 8 0x00 55 spi1dl b i t 7654321b i t 0 0x00 56 spi1mh bit 15 14 13 12 11 10 9 bit 8 0x00 57 spi1ml b i t 7654321b i t 0 0x00 58 iica ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 table 4-2. direct-page register summary (sheet 2 of 4) address register name b i t 7654321b i t 0
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 43 0x00 59 iicf mult icr 0x00 5a iicc iicen iicie mst tx txak rsta 0 0 0x00 5b iics tcf iaas busy arbl 0 srw iicif rxak 0x00 5c iicd data 0x00 5d iicc2 gcaen adext 0 0 0 ad10 ad9 ad8 0x00 5e ? 0x00 5f reserved ? ? ? ? ? ? ? ? 0x00 60 tpm2sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 61 tpm2cnth bit 15 14 13 12 11 10 9 bit 8 0x00 62 tpm2cntl bit 7654321bit 0 0x00 63 tpm2modh bit 15 14 13 12 11 10 9 bit 8 0x00 64 tpm2modl bit 7654321bit 0 0x00 65 tpm2c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 66 tpm2c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 67 tpm2c0vl b i t 7654321b i t 0 0x00 68 tpm2c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 69 tpm2c1vh bit 15 14 13 12 11 10 9 bit 8 0x00 6a tpm2c1vl b i t 7654321b i t 0 0x00 6b reserved ? ? ? ? ? ? ? ? 0x00 6c rtcsc rtif rtclks rtie rtcps 0x00 6d rtccnt rtccnt 0x00 6e rtcmod rtcmod 0x00 6f reserved ? ? ? ? ? ? ? ? 0x00 70 spi2c1 spie spe sptie mstr cpol cpha ssoe lsbfe 0x00 71 spi2c2 spmie spimode 0 modfen bidiroe 0 spiswai spc0 0x00 72 spi2br 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 0x00 73 spi2s sprf spmf sptef modf 0 0 0 0 0x00 74 spi2dh bit 15 14 13 12 11 10 9 bit 8 0x00 75 spi2dl b i t 7654321b i t 0 0x00 76 spi2mh bit 15 14 13 12 11 10 9 bit 8 0x00 77 spi2ml b i t 7654321b i t 0 0x00 78 ? 0x00 79 reserved ? ? ? ? ? ? ? ? 0x00 80 usbctl0 usbreset usbpu usbresmen lpresf ? usbvren ? usbphyen 0x00 81 ? 0x00 87 reserved ? ? ? ? ? ? ? ? 0x00 88 perid 0 0 id5 id4 id3 id2 id1 id0 0x00 89 idcomp 1 1 nid5 nid4 nid3 nid2 nid1 nid0 0x00 8a rev rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 0x00 8b ? 0x00 8f reserved ? ? ? ? ? ? ? ? 0x00 90 intstat stall f ? resumef sleepf tokdnef softokf errorf usbrstf 0x00 91 intenb stall ? resume sleep tokdne softok error usbrst table 4-2. direct-page register summary (sheet 3 of 4) address register name b i t 7654321b i t 0
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 44 freescale semiconductor high-page registers, shown in table 4-3 , are accessed much less often than other i/o and control registers so they have been located outside the dire ct addressable memory space, starting at 0x1800. 0x00 92 errstat btserrf ? buferrf btoerrf dfn8f crc16f crc5f piderrf 0x00 93 errenb btserr 0 buferr btoerr dfn8 crc16 crc5 piderr 0x00 94 stat endp in odd 0 0 0x00 95 ctl ? ? tsuspend ? ? cresume oddrst usben 0x00 96 addr ? addr6 addr5 addr4 addr3 addr2 addr1 addr0 0x00 97 frmnuml frm7 frm6 frm5 frm4 frm3 frm2 frm1 frm0 0x00 98 frmnumh 0 0 0 0 0 frm10 frm9 frm8 0x00 99 ? 0x00 9c reserved ? ? ? ? ? ? ? ? 0x00 9d epctl0 ? ? 0 epctldis eprxen eptxen epstall ephshk 0x00 9e epctl1 ? ? 0 epctldis eprxen eptxen epstall ephshk 0x00 9f epctl2 ? ? 0 epctldis eprxen eptxen epstall ephshk 0x00 a0 epctl3 ? ? 0 epctldis eprxen eptxen epstall ephshk 0x00 a1 epctl4 ? ? 0 epctldis eprxen eptxen epstall ephshk 0x00 a2 epctl5 ? ? 0 epctldis eprxen eptxen epstall ephshk 0x00 a3 epctl6 ? ? 0 epctldis eprxen eptxen epstall ephshk 0x00 a4 ? 0x00 af reserved ? ? ? ? ? ? ? ? table 4-3. high-page register summary (sheet 1 of 2) addressregister namebit 7654321bit 0 0x1800 srs por pin cop ilop 0loclvd ? 0x1801 sbdfr 0 0 0 0 0 0 0bdfr 0x1802 sopt1 copt stope ? 0 0 ? ? 0x1803 sopt2 copclks copw 0 0 0 spi1fe spi2fe acic 0x1804 ? 0x1805 reserved ? ? ? ? ? ? ? ? 0x1806 sdidh ? ? ? ? id11 id10 id9 id8 0x1807 sdidl id7 id6 id5 id4 id3 id2 id1 id0 0x1808 reserved ? ? ? ? ? ? ? ? 0x1809 spmsc1 lv w f lv wac k lv w i e lv d r e lv d s e lv d e 0 1 bgbe 0x180a spmsc2 ? ? lvdv lvwv ppdf ppdack ? ppdc 0x180b ? 0x180f reserved ? ? ? ? ? ? ? ? 0x1810 dbgcah bit 15 14 13 12 11 10 9 bit 8 0x1811 dbgcal bit 7654321bit 0 0x1812 dbgcbh bit 15 14 13 12 11 10 9 bit 8 0x1813 dbgcbl bit 7654321bit 0 0x1814 dbgfh bit 15 14 13 12 11 10 9 bit 8 0x1815 dbgfl bit 7654321bit 0 table 4-2. direct-page register summary (sheet 4 of 4) address register name b i t 7654321b i t 0
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 45 0x1816 dbgc dbgen arm tag brken rwa rwaen rwb rwben 0x1817 dbgt trgsel begin 0 0 trg3 trg2 trg1 trg0 0x1818 dbgs af bf armf 0 cnt3 cnt2 cnt1 cnt0 0x1819 ? 0x181f reserved ? ? ? ? ? ? ? ? 0x1820 fcdiv divld prdiv8 div5 div4 div3 div2 div1 div0 0x1821 fopt keyen fnored 0 0 0 0 sec01 sec00 0x1822 reserved ? ? ? ? ? ? ? ? 0x1823 fcnfg 0 0 keyacc 0 0 0 0 0 0x1824 fprot fps7 fps6 fps5 fps4 f ps3 fps2 fps1 fpdis 0x1825 fstat fcbef fccf fpviol faccerr 0 fblank 0 0 0x1826 fcmd fcmd7 fcmd6 fcmd5 fcmd4 fcmd3 fcmd2 fcmd1 fcmd0 0x1827 ? 0x183f reserved ? ? ? ? ? ? ? ? 0x1840 ptape ? ? ptape5 ? ? ? ? ptape0 0x1841 ptase ? ? ptase5 ? ? ? ? ptase0 0x1842 ptads ? ?ptads5 ? ? ? ?ptads0 0x1843 reserved ? ? ? ? ? ? ? ? 0x1844 ptbpe ? ? ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 0x1845 ptbse ? ? ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 0x1846 ptbds ? ? ptbds5 ptbds4 ptbds3 ptbds2 ptbds1 ptbds0 0x1847 reserved ? ? ? ? ? ? ? ? 0x1848 ptcpe ? ? ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 0x1849 ptcse ? ? ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 0x184a ptcds ? ? ptcds5 ptcds4 ptcds3 ptcds2 ptcds1 ptcds0 0x184b reserved ? ? ? ? ? ? ? ? 0x184c ptdpe ptdpe7 ? ? ? ? ptdpe2 ptdpe1 ptdpe0 0x184d ptdse ptdse7 ? ? ? ? ptdse2 ptdse1 ptdse0 0x184e ptdds ptdds7 ? ? ? ? ptdds2 ptdds1 ptdds0 0x184f reserved ? ? ? ? ? ? ? ? 0x1850 ptepe ptepe7 ptepe6 ptepe5 ptepe4 ptepe3 ptepe2 ptepe1 ptepe0 0x1851 ptese ptese7 ptese6 ptese5 ptese4 ptese3 ptese2 ptese1 ptese0 0x1852 pteds pteds7 pteds6 pteds5 pteds4 pteds3 pteds2 pteds1 pteds0 0x1853 reserved ? ? ? ? ? ? ? ? 0x1854 ptfpe ? ptfpe6 ptfpe5 ptfpe4 ? ? ptfpe1 ptfpe0 0x1855 ptfse ? ptfse6 ptfse5 ptfse4 ? ? ptfse1 ptfse0 0x1856 ptfds ? ptfds6 ptfds5 ptfds4 ? ? ptfds1 ptfds0 0x1857 reserved ? ? ? ? ? ? ? ? 0x1858 ptgpe ? ? ptgpe5 ptgpe4 ptgpe3 ptgpe2 ptgpe1 ptgpe0 0x1859 ptgse ? ? ptgse5 ptgse4 ptgse3 ptgse2 ptgse1 ptgse0 0x185a ptgds ? ? ptgds5 ptgds4 ptgds3 ptgds2 ptgds1 ptgds0 0x185b ? 0x185f reserved ? ? ? ? ? ? ? ? table 4-3. high-page register summary (sheet 2 of 2) addressregister namebit 7654321bit 0
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 46 freescale semiconductor nonvolatile flash regi sters, shown in table 4-4 , are located in the flash me mory. these registers include an 8-byte backdoor key which optionall y can be used to gain access to secure memory resources. during reset events, the contents of nvprot and nvopt in the nonvolatile register area of the flash memory are transferred into corresponding fprot and fopt wo rking registers in the high-page registers to control security and block protection options. provided the key enable (keyen) bit is 1, the 8-by te comparison key can be used to temporarily disengage memory security. this ke y mechanism can be accessed only th rough user code running in secure memory. (a security key cannot be entered directly through ba ckground debug commands.) this security key can be disabled completely by programming the keyen bit to 0. if th e security key is disabled, the only way to disengage security is by mass erasing the flash if needed (normally throug h the background debug interface) and verifying that flash is blank. to a void returning to secure mode after the next reset, program the security bits (sec01:se c00) to the unsecured state (1:0). 4.3 ram (system ram) the MC9S08JM16 series includes static ram. th e locations in ram below 0x0100 can be accessed using the more efficient direct addr essing mode, and any single bit in this area can be accessed with the bit manipulation instructions (bclr, bset, brclr, and brset). locating the most frequently accessed program variables in this area of ram is preferred. the ram retains data when the mcu is in low-power wait, stop2, or st op3 mode. at power-on, the contents of ram are uninitialized. ram data is unaffected by any rese t provided that the supply voltage does not drop below the minimum value for ram retention. for compatibility with m68hc05 mcus, the hcs 08 resets the stack pointer to 0x00ff. in the MC9S08JM16 series, re-initialize the st ack pointer to the top of the ra m so the direct-page ram can be used for frequently accessed ram vari ables and bit-addressable program variables. include the following 2-instruction sequence in your reset initialization routine (where ramlast is e quated to the highest address of the ram in the freescale-provided equate file). 1 this reserved bit must always be written to 0. table 4-4. nonvolatile register summary addressregister namebit 7654321bit 0 0xffae reserved to store ftrim 0 0 0 0 0 0 0ftrim 0xffaf reserved to store mcgtrim trim 0xffb0 ? 0xffb7 nvbackkey 8-byte comparison key 0xffb8 ? 0xffbc reserved ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0xffbd nvprot fps7 fps6 fps5 fps4 f ps3 fps2 fps1 fpdis 0xffbe reserved ? ? ? ? ? ? ? ? 0xffbf nvopt keyen fnored 0 0 0 0 sec01 sec00
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 47 ldhx #ramlast+1 ;point one past ram txs ;sp<-(h:x-1) when security is enabled, the ram is considered a secure memory resource a nd is not accessible through bdm or through code executing from non-secure memory. see section 4.6, ?security ,? for a detailed description of the security feature. 4.4 usb ram usb ram is discussed in detail in chapter 17, ?universal serial bus device controller (s08usbv1) .? 4.5 flash flash memory is used for program storage. in-circu it programming allows the operating program to be loaded into the flash memory after final assembly of the a pplication product. it is possible to program the entire array through the single-wire background debug in terface. because no special voltages are needed for flash erase and programming operations, in-application programming is also possible through other software-controlled communication path s. for a more detailed discussi on of in-circuit a nd in-application programming, refer to the hcs08 family reference manual, volume i, freescale semiconductor document order number hcs08rmv1. 4.5.1 features features of the flash memory include: ? flash size ? MC9S08JM16 ? 16, 384 bytes (32 pages of 512 bytes each) ? mc9s08jm8 ? 8,192 bytes (16 pages of 512 bytes each) ? single power supply program and erase ? command interface for fast program and erase operation ? up to 100,000 program/erase cycles at typical voltage and temperature ? flexible block protection ? security feature for flash and ram ? auto power-down for low-frequency read accesses 4.5.2 program and erase times before any program or erase comma nd can be accepted, the flash clock di vider register (fcdiv) must be written to set the internal clock for the flash module to a frequency (f fclk ) between 150 khz and 200 khz (see section 4.7.1, ?flash clock di vider register (fcdiv).?) this register can be written only once, so normally this write is done during re set initialization. fcdiv cannot be written if the access error flag, faccerr in fstat, is set. the user must ensure th at faccerr is not set be fore writing to the fcdiv register. one period of the resulting clock (1/f fclk ) is used by the command processor to time program
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 48 freescale semiconductor and erase pulses. an integer number of these timing pul ses are used by the command processor to complete a program or erase command. table 4-5 shows program and erase times . the bus clock fre quency and fcdiv determine the frequency of fclk (f fclk ). the time for one cycle of fclk is t fclk =1/f fclk . the times are shown as a number of cycles of fclk and as an ab solute time for the case where t fclk =5 s. program and erase times shown include overhead for the command state machine and enabling and disablin g of program and erase voltages. 4.5.3 program and erase command execution the steps for executing any of the co mmands are listed below. the fcdiv register must be initialized and any error flags cleared before beginning command execution. the command execution steps are: 1. write a data value to an address in the flash arra y. the address and data in formation from this write is latched into the flash interface. this write is a required first step in any command sequence. for erase and blank check commands, th e value of the data is not impor tant. for page erase commands, the address may be any address in the 512-byte page of flas h to be erased. for mass erase and blank check commands, the address can be any address in the flash memory. whole pages of 512 bytes are the smallest block of flash th at may be erased. in the 60k vers ion, there are two instances where the size of a block that is accessible to the user is less than 512 bytes: the first page following ram, and the first page following the high page registers. these pages are overlapped by the ram and high page registers respectively. note do not program any byte in the flash mo re than once after a successful erase operation. reprogramming bits to a byt e which is already programmed is not allowed without first er asing the page in which th e byte resides or mass erasing the entire flash memory. pr ogramming without first erasing may disturb data stored in the flash. 2. write the command code for the desired command to fcmd. the five valid commands are blank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). the command code is latched into the command buffer. 3. write a 1 to the fcbef bit in fstat to clear fcbef and launch the command (including its address and data information). a partial command sequence can be aborted manually by writing a 0 to fcbef any time after the write to the memory array and before writing the 1 that clears fcbef and launches the complete command. table 4-5. program and erase times parameter cycles of fclk time if fclk = 200 khz byte program 9 45 s byte program (burst) 4 20 s 1 1 excluding start/end overhead page erase 4000 20 ms mass erase 20,000 100 ms
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 49 aborting a command in this way sets the faccerr acc ess error flag which must be cleared before starting a new command. a strictly monitored procedure must be obeyed or the command will not be accepted. this minimizes the possibility of any unintended change s to the flash memory contents. the command complete flag (fccf) indicates when a command is complete. the comma nd sequence must be completed by clearing fcbef to launch the command. figure 4-2 is a flowchart for executing all of the commands except for burst programming. the fcdiv register must be initialized before using a ny flash commands. this must be done once following a reset. figure 4-2. flash program and erase flowchart 4.5.4 burst program execution the burst program command is used to program sequential bytes of da ta in less time than would be required using the standard program command. this is possible because the high vol tage to the flash array does not need to be disabled betw een program operations. ordinarily, when a program or erase command start write to flash to buffer address and data write command to fcmd no yes fpviol or write 1 to fcbef to launch command and clear fcbef 2 1 0 fccf? error exit done 0 faccerr? clear error faccerr? write to fcdiv 1 1 flash program and erase flow 1 required only once after reset. 2 wait at least four bus cycles before checking fcbef or fccf.
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 50 freescale semiconductor is issued, an internal charge pum p associated with the flash memory must be enabled to supply high voltage to the array. upon completion of the comma nd, the charge pump is turned off. when a burst program command is issued, the charge pump is enable d and then remains enabled after completion of the burst program operation if th ese two conditions are met: ? the next burst program command has been que ued before the current program operation has completed. ? the next sequential address se lects a byte on the same physical row as the current byte being programmed. a row of flash memory consists of 64 bytes. a byte within a row is selected by addresses a5 through a0. a new row begins wh en addresses a5 through a0 are all zero. the first byte of a series of sequential bytes being pr ogrammed in burst mode will take the same amount of time to program as a byte progr ammed in standard mode. subsequent bytes will program in the burst program time provided that the condi tions above are met. in the case the next sequential address is the beginning of a new row, the pr ogram time for that byte will be the st andard time instead of the burst time. this is because the high voltage to the array must be disabled and then enabled again. if a new burst command has not been queued before the current command complete s, then the charge pump will be disabled and high voltage will be removed from the array.
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 51 figure 4-3. flash burst program flowchart 4.5.5 access errors an access error occurs when the command execution protocol is violated. any of the following specif ic actions will cause the access error fl ag (faccerr) in fstat to be set. faccerr must be cleared by writing a 1 to faccerr in fstat before any command can be processed. ? writing to a flash address before the internal fl ash clock frequency has been set by writing to the fcdiv register ? writing to a flash address whil e fcbef is not set (a new comm and cannot be started until the command buffer is empty) 1 0 fcbef? start write to flash to buffer address and data write command (0x25) to fcmd no yes fpvio or write 1 to fcbef to launch command and clear fcbef 2 no yes new burst command? 1 0 fccf? error exit done 1 0 faccerr? clear error faccerr? write to fcdiv 1 flash burst program flow 1 required only once after reset. 2 wait at least four bus cycles before checking fcbef or fccf.
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 52 freescale semiconductor ? writing a second time to a flash address before launching the previo us command (there is only one write to flash for every command) ? writing a second time to fcmd before launching the previous command (there is only one write to fcmd for every command) ? writing to any flash control register other than fcmd afte r writing to a flash address ? writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to fcmd ? accessing (read or write) any flas h control register other than th e write to fstat (to clear fcbef and launch the command) after writing the command to fcmd. ? the mcu enters stop mode while a program or er ase command is in progress (the command is aborted) ? writing the byte program, burst program, or pa ge erase command code (0x20, 0x25, or 0x40) with a background debug command while the mcu is secured (the background debug controller can only do blank check and mass erase commands when the mcu is secure) ? writing 0 to fcbef to cancel a partial command 4.5.6 flash block protection the block protection feature prevents the protected re gion of flash from program or erase changes. block protection is controlled through the flash protection register (fprot). when enabled, block protection begins at any 512 byte boundary below th e last address of flash, 0xffff. (see section 4.7.4, ?flash protection register (fprot and nvprot) .?) after exit from reset, fprot is loaded with the contents of the nvprot location which is in the nonvolatile register block of the fl ash memory. fprot cannot be changed directly from application software so a runaway program ca nnot alter the block prot ection settings. since nvprot is within the last 512 bytes of flash, if any amount of memory is protect ed, nvprot is itself pr otected and cannot be altered (intentionally or unintenti onally) by the application software. fprot can be written through background debug commands which allows a way to erase and reprogram a protected flash memory. the block protection mechanism is il lustrated below. the fps bits are us ed as the upper bits of the last address of unprotected memory. this address is formed by concatenati ng fps7:fps1 with logic 1 bits as shown. for example, in order to protect the last 8192 bytes of me mory (address 0xe000 through 0xffff), the fps bits must be set to 1101 111 which results in the value 0xdfff as the last address of unprotected memory. in addition to programming the fps bits to the appropriate value, fpdis (bit 0 of nvprot) must be programmed to logic 0 to enable block protection. therefore the value 0xd e must be programmed into nvprot to protect addresses 0xe000 through 0xffff. figure 4-4. block protection mechanism fps7 fps6 fps5 fps4 fps3 fps2 fps1 a15 a14 a13 a12 a11 a10 a9 a8 1 a7 a6 a5 a4 a3 a2 a1 a0 111 11111
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 53 block protection can block-protect an area of flash memory for a boot loader program. this bootloader program then can be used to erase the rest of the flash memory and reprogram it. be cause the bootloader is protected, it remains intact even if mcu power is lost in the middl e of an erase or reprogram operation. 4.5.7 vector redirection whenever any block protection is en abled, the reset and interrupt v ectors will be protected. vector redirection allows users to modify interrupt vector information wit hout unprotecting bootloader and reset vector space. vector redirection is enabled by programming the fnored bit in the nvopt register located at address 0xffbf to zero. fo r redirection to occur, at least so me portion but not all of the flash memory must be block protected by programming the nvprot register located at address 0xffbd. all of the interrupt vectors (memor y locations 0xffc0?0xfffd) are redi rected, though the reset vector (0xfffe:ffff) is not. for example, if 512 bytes of flash are protected, the protected address region is from 0xfe00 through 0xffff. the interrupt vectors (0x ffc0?0xfffd) are redirected to th e locations 0xfdc0?0xfdfd. now, if a tpm1 overflow interrupt is take n for instance, the values in the locations 0xfde0:fde1 are used for the vector instead of the values in the locations 0xffe0:ffe1. this allows the user to reprogram the unprotected portion of the fl ash with new program c ode including new interrupt vector values while leaving the protected area, which include s the default vector locations, unchanged. 4.6 security the MC9S08JM16 series include circuitry to preven t unauthorized access to the contents of flash and ram memory. when security is engaged, flash and ram are considered secure resources. direct-page registers, high-page registers, and the background debug controller are consider ed unsecured resources. programs executing within secure memory have normal access to any mcu memory locations and resources. attempts to access a secure memory lo cation with a program executing from an unsecured memory space or through the background debug interface are bloc ked (writes are ignored and reads return all 0s). security is engaged or disengaged based on the stat e of two nonvolatile register bits (sec01:sec00) in the fopt register. during reset, the contents of th e nonvolatile location nvopt are copied from flash into the working fopt register in hi gh-page register space. a user engages security by programming the nvopt location which can be done at the same time the flash memory is programmed. the 1:0 state disengages security and the other thr ee combinations engage security. no tice the erased state (1:1) makes the mcu secure. during development, whenever the fl ash is erased, immediatel y program the sec00 bit to 0 in nvopt, so sec01:sec00 = 1:0. this woul d allow the mcu to remain unsecured after a subsequent reset. the on-chip debug module cannot be enabled while the mcu is secure. the separate background debug controller can still be used for background memory access commands, but the mcu cannot enter active background mode except by holding bkgd/ms low at the rising edge of reset. a user can choose to allow or disallow a securi ty unlocking mechanism through an 8-byte backdoor security key. if the nonvolatile ke yen bit in nvopt/fopt is 0, the b ackdoor key is disabled and there
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 54 freescale semiconductor is no way to disengage security without completely erasing all flash locations . if keyen is 1, a secure user program can temporar ily disengage security by: 1. writing 1 to keyacc in the fcnfg register. this makes the flash module interpret writes to the backdoor comparison key locations (nvbackkey through nvbac kkey+7) as values to be compared against the key rather than as the fi rst step in a flash program or erase command. 2. writing the user-entered key values to the nvbackkey through nvbackkey+7 locations. these writes must be done in order starting with the value for nvbackkey and ending with nvbackkey+7. sthx must not be used for these writes because these writes cannot be done on adjacent bus cycles. user software normally would get the key codes from outside the mcu system through a communication in terface such as a serial i/o. 3. writing 0 to keyacc in the fcnfg register. if the 8-byte key that was just written matches the key stored in the flash locations , sec01:sec00 are automatically ch anged to 1:0 and security will be disengaged until the next reset. the security key can be wr itten only from secure memory (ram or flash), so it cannot be entered through background commands without the coope ration of a secure user program. the backdoor comparison key (nvbackkey through nvbackkey+7) is located in flash memory locations in the nonvolatile register space, so users can program these locations exactly as they would program any other flash memo ry location. the no nvolatile registers are in the same 512-byte block of flash as the reset and interrupt vectors, so block prot ecting that space also block protects the backdoor comparison key. block protec ts cannot be changed from user application programs, so if the vector space is block protected, the backdoor security key mechan ism cannot permanently change the block protect, security settings, or the backdoor key. security can always be disengaged through th e background debug interfac e by taking these steps: 1. disable any block protections by writing fprot. fprot can be written only with background debug commands, not from application software. 2. mass erase flash if necessary. 3. blank check flash. provided flash is completely er ased, security is disenga ged until the next reset. to avoid returning to secure mode after the next reset, program nvopt so sec01:sec00 = 1:0. 4.7 flash registers and control bits the flash module has nine 8-bit regi sters in the high-page register space, three locations in the nonvolatile register space in flash memory which are copied in to three corresponding high-pa ge control registers at reset. there is also an 8-byte comparison key in flash memory. refer to table 4-3 and table 4-4 for the absolute address assignments for all fl ash registers. this section refers to registers and control bits only by their names. a freescale-provided equa te or header file normally is used to translate these names into the appropriate absolute addresses.
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 55 4.7.1 flash clock divider register (fcdiv) bit 7 of this register is a read-onl y status flag. bits 6 through 0 may be read at any time but can be written only one time. before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. if prdiv8 = 0 ? f fclk = f bus ([div5:div0] + 1) eqn. 4-1 if prdiv8 = 1 ? f fclk = f bus (8 ([div5:div0] + 1)) eqn. 4-2 table 4-7 shows the appropriate values for prdiv8 and div5:div0 for sele cted bus frequencies. 76543210 rdivld prdiv8 div5 div4 div3 div2 div1 div0 w r e s e t00000000 = unimplemented or reserved figure 4-5. flash clock divider register (fcdiv) table 4-6. fcdiv regist er field descriptions field description 7 divld divisor loaded status flag ? when set, this read-only status flag indicates that the fcdiv register has been written since reset. reset clears this bit and the first write to this register causes this bit to become set regardless of the data written. 0 fcdiv has not been written since reset; erase and program operations disabled for flash. 1 fcdiv has been written since reset; erase and program operations enabled for flash. 6 prdiv8 prescale (divide) flash clock by 8 0 clock input to the flash clock divider is the bus rate clock. 1 clock input to the flash clock divider is the bus rate clock divided by 8. 5:0 div[5:0] divisor for flash clock divider ? the flash clock divider divides the bus rate clock (or the bus rate clock divided by 8 if prdiv8 = 1) by the value in the 6-bit div5:div0 field plus one. the resulting frequency of the internal flash clock must fall within the range of 200 khz to 150 khz for proper flash operations. program/erase timing pulses are one cycle of this internal flash clock which corresponds to a range of 5 s to 6.7 s. the automated programming logic uses an integer number of these pulses to complete an erase or program operation. see equation 4-1 , equation 4-2 , and ta bl e 4 - 6 .
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 56 freescale semiconductor 4.7.2 flash options register (fopt and nvopt) during reset, the contents of th e nonvolatile location nvopt are copi ed from flash into fopt. bits 5 through 2 are not used and always read 0. this register may be read at a ny time, but writes have no meaning or effect. to change the value in this register, erase and reprogram the nvopt location in flash memory as usual and then issue a new mcu reset. table 4-7. flash clock divider settings f bus prdiv8 (binary) div5:div0 (decimal) f fclk program/erase timing pulse (5 s min, 6.7 s max) 24 mhz 1 14 200 khz 5 s 20 mhz 1 12 192.3 khz 5.2 s 10 mhz 0 49 200 khz 5 s 8 mhz 0 39 200 khz 5 s 4 mhz 0 19 200 khz 5 s 2 mhz 0 9 200 khz 5 s 1 mhz 0 4 200 khz 5 s 200 khz 0 0 200 khz 5 s 150 khz 0 0 150 khz 6.7 s 76543210 r keyen fnored 0 0 0 0 sec01 sec00 w reset this register is loaded from nonvolatile location nvopt during reset. = unimplemented or reserved figure 4-6. flash options register (fopt) table 4-8. fopt register field descriptions field description 7 keyen backdoor key mechanism enable ? when this bit is 0, the backdoor key mechanism cannot be used to disengage security. the backdoor key mechanism is accessible only from user (secured) firmware. bdm commands cannot be used to write key comparison values that would unlock the backdoor key. for more detailed information about the backdoor key mechanism, refer to section 4.6, ?security .? 0 no backdoor key access allowed. 1 if user firmware writes an 8-byte value that matches the nonvolatile backdoor key (nvbackkey through nvbackkey+7 in that order), security is te mporarily disengaged until the next mcu reset. 6 fnored vector redirection disable ? when this bit is 1, then vector redirection is disabled. 0 vector redirection enabled. 1 vector redirection disabled. 1:0 sec0[1:0] security state code ? this 2-bit field determines the security state of the mcu as shown in ta bl e 4 - 9 . when the mcu is secure, the contents of ram and flash memo ry cannot be accessed by instructions from any unsecured source including the background debug interface. for more detailed information about security, refer to section 4.6, ?security .?
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 57 sec01:sec00 changes to 1:0 after successful backdoor key entry or a successful blank check of flash. 4.7.3 flash configurat ion register (fcnfg) bits 7 through 5 may be read or wri tten at any time. bits 4 through 0 always read 0 and cannot be written. 4.7.4 flash protection register (fprot and nvprot) during reset, the contents of the nonvolatile location nvprot are copied from flash into fprot. bits 0, 1, and 2 are not used and each always reads as 0. this register may be r ead at any time, but user program writes have no meaning or effect. bac kground debug commands can write to fprot. table 4-9. security states sec01:sec00 description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure 76543210 r0 0 keyacc 00000 w r e s e t00000000 = unimplemented or reserved figure 4-7. flash configur ation register (fcnfg) table 4-10. fcnfg register field descriptions field description 5 keyacc enable writing of access key ? this bit enables writing of the backdoor comparison key. for more detailed information about the backdoor key mechanism, refer to section 4.6, ?security .? 0 writes to 0xffb0?0xffb7 are interpreted as the start of a flash programming or erase command. 1 writes to nvbackkey (0xffb0?0xffb7) are interpreted as comparison key writes. 76543210 r fps7 fps6 fps5 fps4 fps3 fps2 fps1 fpdis w 11111111 reset this register is loaded from nonvolatile location nvprot during reset. 1 background commands can be used to change the contents of these bits in fprot. figure 4-8. flash protection register (fprot)
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 58 freescale semiconductor 4.7.5 flash status register (fstat) bits 3, 1, and 0 always read 0 and writes have no meani ng or effect. the remaining fi ve bits are status bits that can be read at any time. writes to these bits have special meanings that are discussed in the bit descriptions. table 4-11. fprot register field descriptions field description 7:1 fps[7:1] flash protect select bits ? when fpdis = 0, this 7-bit field determ ines the ending address of unprotected flash locations at the high address end of the flash. pr otected flash locations cannot be erased or programmed. 0 fpdis flash protection disable 0 flash block specified by fps[7:1] is block protected (program and erase are not allowed). 1 no flash block is protected. 76543210 r fcbef fccf fpviol faccerr 0fblank0 0 w r e s e t11000000 = unimplemented or reserved figure 4-9. flash status register (fstat) table 4-12. fstat regist er field descriptions field description 7 fcbef flash command buffer empty flag ? the fcbef bit is used to launch commands. it also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. the fcbef bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. only burst program commands can be buffered. 0 command buffer is full (not ready for additional commands). 1 a new burst program command may be written to the command buffer. 6 fccf flash command complete flag ? fccf is set automatically when t he command buffer is empty and no command is being processed. fccf is cleared automatically when a new co mmand is started (by writing 1 to fcbef to register a command). writing to fccf has no meaning or effect. 0 command in progress. 1 all commands complete. 5 fpviol protection violation flag ? fpviol is set automatically when fcbef is cleared to register a command that attempts to erase or program a location in a protecte d block (the erroneous command is ignored). fpviol is cleared by writing a 1 to fpviol. 0 no protection violation. 1 an attempt was made to erase or program a protected location.
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 59 4.7.6 flash command register (fcmd) only five command codes are recognized in normal us er modes as shown in table 4-14 . refer to section 4.5.3, ?program and erase command execution ,? for a detailed discu ssion of flash programming and erase operations. all other command codes are illega l and generate an access error. 4 faccerr access error flag ? faccerr is set automatically when the pr oper command sequence is not obeyed exactly (the erroneous command is ignored). if a program or eras e operation is attempted bef ore the fcdiv register has been initialized, or if the mcu enters stop while a comm and was in progress. for a more detailed discussion of the exact actions that are considered access errors, see section 4.5.5, ?access errors .? faccerr is cleared by writing a 1 to faccerr. writing a 0 to faccerr has no meaning or effect. 0 no access error. 1 an access error has occurred. 2 fblank flash verified as all blank (erased) flag ? fblank is set automatically at the conclusion of a blank check command if the entire flash array was verified to be erased. fblank is cleared by clearing fcbef to write a new valid command. writing to fb lank has no meaning or effect. 0 after a blank check command is completed and fccf = 1, fblank = 0 indicates the flash array is not completely erased. 1 after a blank check command is completed and fccf = 1, fblank = 1 indicates the flash array is completely erased (all 0xff). 76543210 r00000000 w fcmd7 fcmd6 fcmd5 fcmd4 fcmd3 fcmd2 fcmd1 fcmd0 reset00000000 figure 4-10. flash command register (fcmd) table 4-13. fcmd register field descriptions field description fcmd[7:0] flash command bits ? see ta b l e 4 - 1 4 table 4-14. flash commands command fcmd equate file label blank check 0x05 mblank byte program 0x20 mbyteprog byte program ? burst mode 0x25 mburstprog page erase (512 bytes/page) 0x40 mpageerase mass erase (all flash) 0x41 mmasserase table 4-12. fstat register fi eld descriptions (continued) field description
chapter 4 memory MC9S08JM16 series data sheet, rev. 2 60 freescale semiconductor it is not necessary to perform a blank check command after a mass erase operation. blank check is required only as part of the secu rity unlocking mechanism.
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 61 chapter 5 resets, interrupts, and system configuration 5.1 introduction this chapter discusses basic reset a nd interrupt mechanisms and the vari ous sources of reset and interrupts in the MC9S08JM16 series. some inte rrupt sources from peripheral modules are discussed in greater detail in other chapters of this reference manual. this chapter gathers basic inform ation about all reset and interrupt sources in one place for easy reference. a few reset and interrupt sources, including the computer operating properly (cop) watchdog, are not part of on-chip peripheral syst ems with their ow n sections but are part of the system control logic. 5.2 features reset and interrupt features include: ? multiple sources of reset for flexible sy stem configuration an d reliable operation ? reset status register (srs) to indicate source of most recent reset ? separate interrupt vectors for each module (reduces polling overhead) (see table 5-1 ) 5.3 mcu reset resetting the mcu provides a way to start processing from a known set of initial conditions. during reset, most control and status registers ar e forced to initial values and the program counter is loaded from the reset vector (0xfffe:0xffff). on-chip peripheral m odules are disabled and i/o pins are initially configured as general-purpose high-impedance input s with pullup devices disa bled. the i bit in the condition code register (ccr) is set to block maskable interrupts, so the user program has a chance to initialize the stack pointer (sp) and system c ontrol settings. sp is forced to 0x00ff at reset. the MC9S08JM16 series has eight sources for reset: ? power-on reset (por) ? low-voltage detect (lvd) ? computer operating properly (cop) timer ? illegal opcode detect (ilop) ? illegal address detect (ilad) ? background debug forced reset ? external reset pin (reset) ? clock generator loss of lock and loss of clock reset (loc)
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 62 freescale semiconductor each of these sources, with the ex ception of the background debug forced reset, has an associated bit in the system reset status (srs) register. 5.4 computer operating properly (cop) watchdog the cop watchdog is used to force a system reset when the application software fails to execute as expected. to prevent a system reset from the cop time r (when it is enabled), ap plication software must reset the cop counter periodically. if the application pr ogram gets lost and fails to reset the cop counter before it times out, a sy stem reset is generated to force the system back to a known starting point. after any reset, the cop watchdog is enabled (see section 5.7.4, ?system options register 1 (sopt1) ,? for additional information). if the cop watchdog is not used in an a pplication, it can be disabled by clearing copt bits in sopt1. the cop counter is reset by writing 0x55 and 0xaa (i n this order) to the address of srs during the selected timeout period. writes do not affect the data in the read-only srs. as soon as the write sequence is done, the cop timeout pe riod is restarted. if the pr ogram fails to do this duri ng the time-out period, the mcu will reset. also, if any valu e other than 0x55 or 0xaa is written to srs, the mcu is immediately reset. the copclks bit in sopt2 (see section 5.7.5, ?system options register 2 (sopt2) ,? for additional information) selects the clock sour ce used for the cop timer. the cloc k source options are either the bus clock or an internal 1 khz clock source. with each clock source, th ere are three associated time-outs controlled by the copt bits in sopt1. table 5-6 summaries the control func tions of the copclks and copt bits. the cop watchdog defaults to operation fr om the 1 khz clock source and the longest time-out (2 10 cycles). when the bus clock source is selected, windowed cop operation is available by setting copw in the sopt2 register. in this mode, writes to the srs register to clear the co p timer must occur in the last 25% of the selected timeout period. a premature write immediately resets the mcu. when the 1 khz clock source is selected, windowed cop operation is not available. the cop counter is initiali zed by the first writes to the sopt1 and sopt2 regist ers and after any system reset. subsequent writes to sopt1 and sopt2 have no effect on cop operation. even if the application will use the reset default settings of copt, copclks, and copw bi ts, the user must write to the write-once sopt1 and sopt2 registers dur ing reset initialization to lock in the settings. this will prevent accidental changes if the application program gets lost. the write to srs that services (cle ars) the cop counter must not be pl aced in an interrupt service routine (isr) because the isr could continue to be executed periodically even if the main application program fails. if the bus clock source is selected, the cop coun ter does not increment while the mcu is in background debug mode or while the system is in stop mode . the cop counter resumes when the mcu exits background debug mode or stop mode. if the 1 khz clock source is selected, the cop counter is re-initialized to zero upon entry to background debug mode or stop mode and begins from zero upon exit from bac kground debug mode or stop mode.
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 63 5.5 interrupts interrupts provide a way to save the current cpu status and registers, ex ecute an interrupt service routine (isr), and then restore the cpu status so processing resumes where it left off before the interrupt. other than the software interrupt (swi), which is a program instruction, interrupts are caus ed by hardware events such as an edge on the irq pin or a timer-overflow event. the debug module can also generate an swi under certain ci rcumstances. if an event occurs in an enabled interrupt source, an associated read-only status flag will become set. the cpu will not respond until and unless the local interrupt enable is a logic 1 to enable the interrupt. the i bit in the ccr is 0 to allow interrupts. the global inte rrupt mask (i bit) in the ccr is initially set after reset which masks (prevents) all maskable interrupt s ources. the user program in itializes the stack pointer and performs other system setup before clearing the i bit to allo w the cpu to respond to interrupts. when the cpu receives a qua lified interrupt request, it completes the current in struction before responding to the interrupt. the interrupt sequence obeys the sa me cycle-by-cycle sequence as the swi instruction and consists of: ? saving the cpu registers on the stack ? setting the i bit in the ccr to mask further interrupts ? fetching the interrupt vector for the highest-priority interrupt that is currently pending ? filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations while the cpu is responding to the interrupt, the i bit is automatically set to avoid the possibility of another interrupt interrupting the isr itself (this is called nesting of interrupts). normally, the i bit is restored to 0 when the ccr is restor ed from the value stacked on entry to the isr. in rare cases, the i bit may be cleared inside an isr (after clearing the status flag that generated the interrupt) so that other interrupts can be serviced without waiting for the fi rst service routine to finish. this practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difficult to debug. the interrupt service routine ends wi th a return-from-interrupt (rti) in struction which restores the ccr, a, x, and pc registers to their pre-interrupt values by reading the previously saved information off the stack. note for compatibility with the m68hc08, the h register is not automatically saved and restored. push h onto the stack at the star t of the interrupt service routine (isr) and restore it immediately before the rti that is used to return from the isr. if two or more interrupts ar e pending when the i bit is cleared, the hi ghest priority source is serviced first (see table 5-1 ).
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 64 freescale semiconductor 5.5.1 interrupt stack frame figure 5-1 shows the contents and organization of a stack frame. before the interrupt, the stack pointer (sp) points at the next av ailable byte location on the stack. the curr ent values of cpu registers are stored on the stack starting with the low-order byte of the program counter (pcl) and ending with the ccr. after stacking, the sp points at the next avai lable location on the stack which is the address that is one less than the address where the ccr was saved. the pc value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. figure 5-1. interrupt stack frame when an rti instruction is executed, these values are recovered from the stack in reverse order. as part of the rti sequence, the cpu fills the instruction pipeline by reading th ree bytes of program information, starting from the pc address recovered from the stack. the status flag causing the interrupt must be acknow ledged (cleared) before returning from the isr. typically, the flag must be cleared at the beginning of th e isr, so that if another interrupt is generated by this same source, it will be registered to be serviced after completion of the current isr. 5.5.2 external interrupt request (irq) pin external interrupts are managed by the irqsc status and control register. when the irq function is enabled, synchronous logic m onitors the pin for edge- only or edge-and-level events. when the mcu is in stop mode and system clocks are shut down, a separate asynchronous path is used so the irq (if enabled) can wake the mcu. 5.5.2.1 pin configuration options the irq pin enable (irqpe) control bi t in irqsc must be 1 for the irq pi n to act as the interrupt request (irq) input. as an irq input, the user can choose th e polarity of edges or le vels detected (irqedg), whether the pin detects edges-only or edges and levels (irqmod), and whether an event causes an interrupt or only sets the irqf fl ag which can be polled by software. condition code register accumulator index register (low byte x) program counter high * high byte (h) of index regist er is not automatically stacked. * program counter low 70 unstacking order stacking order 5 4 3 2 1 1 2 3 4 5 toward lower addresses toward higher addresses sp before sp after interrupt stacking the interrupt
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 65 the irq pin, when enabled, defaults to use an intern al pull device (irqpdd = 0), the device is a pullup or pulldown depending on the polarity chosen. if the user desires to use an external pullup or pulldown, the irqpdd can be written to a 1 to turn off the internal device. bih and bil instructions may be used to detect the level on the irq pin when the pin is configured to act as the irq input. note this pin does not contain a clamp diode to v dd and must not be driven above v dd . the voltage measured on the in ternally pulled up irq pin may be as low as v dd ? 0.7 v. the internal gates c onnected to this pin are pulled all the way to v dd . 5.5.2.2 edge and level sensitivity the irqmod control bit re-configure the detection logic to detect edge events and pin levels. in this edge detection mode, the irqf status flag becomes set wh en an edge is detected (when the irq pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the irq pin remains at the asserted level. 5.5.3 interrupt vectors, sources, and local masks table 5-1 provides a summary of all interrupt sources. higher-priority sources are located toward the bottom of the table. the high-order byt e of the address for the interrupt service routine is located at the first address in the vector address column, and the lo w-order byte of the address for the interrupt service routine is located at the next higher address. when an interrupt condition occurs, an associated flag bit becomes set. if the associated local interrupt enable is 1, an interrupt request is sent to the cpu. within the cpu, if the global interrupt mask (i bit in the ccr) is 0, the cpu will finish the current instruction, stack th e pcl, pch, x, a, and ccr cpu registers, set the i bit, and then fetch the interru pt vector for the highest priority pending interrupt. processing then continues in the interrupt service routine. table 5-1. vector summary (from lowest to highest priority) vector number address (high/low) vector name module source enable description 31 to 30 0xffc0:ffc1 0xffc2:ffc3 unused vector space (available for user program) 29 0xffc4:ffc5 vrtc system control rtif rtie rtc real-time interrupt 28 0xffc6:ffc7 viic iic iicif iicie iic 27 0xffc8:ffc9 vacmp acmp acf acie acmp 26 0xffca:ffcb vadc adc coco aien adc 25 0xffcc:ffcd vkeyboard kbi kbf kbie keyboard pins
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 66 freescale semiconductor 24 0xffce:ffcf vsci2tx sci2 tdre tc t i e tcie sci2 transmit 23 0xffd0:ffd1 vsci2rx sci2 idle rdrf i l i e r i e sci2 receive 22 0xffd2:ffd3 vsci2err sci2 or nf fe pf o r i e n f i e f e i e pfie sci2 error 21 0xffd4:ffd5 vsci1tx sci1 tdre tc t i e tcie sci1 transmit 20 0xffd6:ffd7 vsci1rx sci1 idle rdrf i l i e r i e sci1 receive 19 0xffd8:ffd9 vsci1err sci1 or nf fe pf o r i e n f i e f e i e pfie sci1 error 18 0xffda:ffdb vtpm2ovf tpm2 tof toie tpm2 overflow 17 0xffdc:ffdd vtpm2ch1 tpm2 ch1f ch1ie tpm2 channel 1 16 0xffde:ffdf vtpm2ch0 tpm2 ch0f ch0ie tpm2 channel 0 15 0xffe0:ffe1 vtpm1ovf tpm1 tof toie tpm1 overflow 14 0xffe2:ffe3 reserved reserved reserved reserved reserved 13 0xffe4:ffe5 reserved reserved reserved reserved reserved 12 0xffe6:ffe7 vtpm1ch3 tpm1 ch3f ch3ie tpm1 channel 3 11 0xffe8:ffe9 vtpm1ch2 tpm1 ch2f ch2ie tpm1 channel 2 10 0xffea:ffeb vtpm1ch1 tpm1 ch1f ch1ie tpm1 channel 1 9 0xffec:ffed vtpm1ch0 tpm1 ch0f ch0ie tpm1 channel 0 8 0xffee:ffef reserved ? ? ? ? 7 0xfff0:fff1 vusb usb stallf resumef sleepf tokdnef softokf errorf usbrstf stall resume sleep tokdne softok error usbrst usb status 6 0xfff2:fff3 vspi2 spi2 sprf modf sptef spmf s p i e s p i e s p t i e spmie spi2 table 5-1. vector summary (from lowest to highest priority) (continued) vector number address (high/low) vector name module source enable description
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 67 5.6 low-voltage detect (lvd) system the MC9S08JM16 series includes a syst em to protect memory contents against low voltage conditions and control mcu system states during supply voltage variations. the system is composed of a power-on reset (por) circuit and an lvd circ uit with a user selectable trip voltage, either high (v lvdh ) or low (v lvdl ). the lvd circuit is enabled when lvde in spmsc1 is high and the trip voltage is selected by lvdv in spmsc2. the lvd is disabled upon ente ring any of the stop modes unless the lvdse bit is set. if lvdse and lvde are both set, then the mcu cannot enter stop2, and the curren t consumption in stop3 with the lvd enabled will be greater. 5.6.1 power-on reset operation when power is initially applied to the mcu, or when the supply voltage drops below the v por level, the por circuit will cause a rese t condition. as the supply voltage rises, the lvd circuit will hold the chip in reset until the supply has risen above the v lvdl level. both the por bit and the lvd bit in srs are set following a por. 5.6.2 lvd reset operation the lvd can be configured to generate a reset upon detection of a low vol tage condition by setting lvdre to 1. after an lvd reset has occurred, the lvd system will hold the mcu in reset until the supply voltage has risen above the level determined by lvdv. the lvd bit in the srs register is set following an lvd reset or por. 5 0xfff4:fff5 vspi1 spi1 sprf modf sptef spmf s p i e s p i e s p t i e spmie spi1 4 0xfff6:fff7 vlol mcg lols lolie mcg loss of lock 3 0xfff8:fff9 vlvd system control lvdf lvdie low-voltage detect 2 0xfffa:fffb virq irq irqf irqie irq pin 1 0xfffc:fffd vswi core swi inst ruction ? software interrupt 0 0xfffe:ffff vreset system control cop lv d reset pin illegal opcode illegal address loc por bdfr c o p e lv d r e ? ilop ilad c m e por watchdog timer low-voltage detect exter nal pin illegal opcode illegal address loss of clock power-on-reset bdm-forced reset table 5-1. vector summary (from lowest to highest priority) (continued) vector number address (high/low) vector name module source enable description
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 68 freescale semiconductor 5.6.3 lvd interrupt operation when a low voltage condition is dete cted and the lvd circuit is configured for interrupt operation (lvde set, lvdie set, and lvdre clear), then lvdf will be set and an lvd interrupt will occur. 5.6.4 low-voltage warning (lvw) the lvd system has a low voltage warn ing flag to indicate the user that the supply voltage is approaching, but is still above, the lvd voltage. the lvw does not ha ve an interrupt associated with it. there are two user selectable trip volta ges for the lvw, one high (v lvwh ) and one low (v lvwl ). the trip voltage is selected by lvwv in spmsc2. 5.7 reset, interrupt, and system control registers and control bits one 8-bit register in the direct page register space a nd eight 8-bit registers in th e high-page register space are related to reset and interrupt systems. refer to the direct-page register summary in chapter 4, ?memory ,? of this data sheet for the absolute address assignments for all registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. some control bits in the sopt1 and spmsc2 registers are related to mode s of operation. although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in chapter 3, ?modes of operation .? 5.7.1 interrupt pin request status and control register (irqsc) this direct-page register includes status and control bits, which are used to configure the irq function, report status, and acknowledge irq events. 76543210 r0 irqpdd irqedg irqpe irqf 0 irqie irqmod w irqack r e s e t00000000 = unimplemented or reserved figure 5-2. interrupt request status and control register (irqsc)
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 69 5.7.2 system reset status register (srs) this register includes seven read-only status flags to indicate the source of the most recent reset. when a debug host forces reset by writing 1 to bdfr in the sbdf r register, none of the status bits in srs will be set. writing any value to this register address clears the cop watchdog timer without affecting the contents of this register. the reset state of these bits depends on what caused the mcu to reset. table 5-2. irqsc regist er field descriptions field description 6 irqpdd interrupt request (irq ) pull device disable ? this read/write control bit is used to disable the internal pullup device when the irq pin is enabled (irqpe = 1) allowing for an external device to be used. 0 irq pull device enabled if irqpe = 1. 1 irq pull device disabled if irqpe = 1. 5 irqedg interrupt request (irq) edge select ? this read/write control bit is used to select the polarity of edges or levels on the irq pin that cause irqf to be set. the irqmod control bit determines whether the irq pin is sensitive to both edges and levels or only edges. when the ir q pin is enabled as the irq input and is configured to detect rising edges, the optional pullup resistor is re-configured as an optional pulldown resistor. 0 irq is falling edge or falling edge/low-level sensitive. 1 irq is rising edge or rising edge/high-level sensitive. 4 irqpe irq pin enable ? this read/write control bit enables the irq pin function. when this bit is set, the irq pin can be used as an interrupt request. 0 irq pin function is disabled. 1 irq pin function is enabled. 3 irqf irq flag ? this read-only status bit indicates when an interrupt request event has occurred. 0 no irq request. 1 irq event detected. 2 irqack irq acknowledge ? this write-only bit is used to acknowledge in terrupt request events (write 1 to clear irqf). writing 0 has no meaning or effect. reads always return 0. if edge-and-level detecti on is selected (irqmod = 1), irqf cannot be cleared while the irq pin remains at its asserted level. 1 irqie irq interrupt enable ? this read/write control bit determines whether irq events generate an interrupt request. 0 interrupt request when irqf set is disabled (use polling). 1 interrupt requested whenever irqf = 1. 0 irqmod irq detection mode ? this read/write control bit selects eith er edge-only detection or edge-and-level detection. see section 5.5.2.2, ?edge and level sensitivity ,? for more details. 0 irq event on falling/rising edges only. 1 irq event on falling/rising edges and low/high levels.
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 70 freescale semiconductor 5.7.3 system background debug force reset register (sbdfr) this register contains a single write-only c ontrol bit. a serial background command such as write_byte must be used to write to sbdfr. attemp ts to write this register from a user program are ignored. reads always return 0x00. 76543210 r por pin cop ilop 0 loc lvd ? w writing any value to srs address clears cop watchdog timer. por10000010 lvr:u0000010 any other reset: 0 (1) (1) (1) 0 (1) 00 u = unaffected by reset 1 any of these reset sources that are active at the time of re set will cause the corresponding bit(s) to be set; bits correspondi ng to sources that are not active at the time of reset will be cleared. figure 5-3. system reset status (srs) table 5-3. srs register field descriptions field description 7 por power-on reset ? reset was caused by the power-on detection logic. because the internal supply voltage was ramping up at the time, the low-voltage reset (lvr) status bit is also set to indicate that the reset occurred while the internal supply was below the lvr threshold. 0 reset not caused by por. 1 por caused reset. 6 pin external reset pin ? reset was caused by an active-low level on the external reset pin. 0 reset not caused by external reset pin. 1 reset came from external reset pin. 5 cop computer operating properly (cop) watchdog ? reset was caused by the cop watchdog timer timing out. this reset source may be blocked by cope = 0. 0 reset not caused by cop timeout. 1 reset caused by cop timeout. 4 ilop illegal opcode ? reset was caused by an attempt to execut e an unimplemented or illegal opcode. the stop instruction is considered illegal if stop is disabled by stope = 0 in the sopt regi ster. the bgnd instruction is considered illegal if active background mode is disabled by enbdm = 0 in the bdcsc register. 0 reset not caused by an illegal opcode. 1 reset caused by an illegal opcode. 2 loc loss-of-clock reset ? reset was caused by a loss of external clock. 0 reset not caused by a loss of external clock. 1 reset caused by a loss of external clock. 1 lv d low voltage detect ? if the lvdre and lvdse bits are set and the supply drops below the lvd trip voltage, an lvd reset will occur. this bit is also set by por. 0 reset not caused by lvd trip or por. 1 reset caused by lvd trip or por.
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 71 5.7.4 system options register 1 (sopt1) this register may be read at any time. bits 3 a nd 2 are unimplemented and always read 0. this is a write-once register so only the first write after reset is honored. any subs equent attempt to write to sopt (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. sopt must be written during the user?s rese t initialization program to set the de sired controls even if the desired settings are the same as the reset settings. 76543210 r00000000 w bdfr 1 r e s e t00000000 = unimplemented or reserved 1 bdfr is writable only through serial back ground debug commands, not from user programs. figure 5-4. system background debug force reset register (sbdfr) table 5-4. sbdfr register field descriptions field description 0 bdfr background debug force reset ? a serial background command such as write_byte may be used to allow an external debug host to force a target system reset. writing logic 1 to this bit forces an mcu reset. this bit cannot be written from a user program. 76543210 r copt stope 00 w r e s e t11010011 = unimplemented or reserved figure 5-5. system options register (sopt1) table 5-5. sopt1 register field descriptions field description 7:6 copt[1:0] cop watchdog timeout ? these write-once bits select the tim eout period of the cop. copt along with copclks in sopt2 defines t he cop timeout period. see ta b l e 5 - 6 . 5 stope stop mode enable ? this write-once bit defaults to 0 after rese t, which disables stop mode. if stop mode is disabled and a user program attempts to execute a stop instruction, an illegal opcode reset is forced. 0 stop mode disabled. 1 stop mode enabled.
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 72 freescale semiconductor 5.7.5 system options register 2 (sopt2) table 5-6. cop configuration options control bits clock source cop window 1 opens (copw = 1) 1 windowed cop operation requires the user to clear the cop timer in the last 25% of the selected timeout period. this column displays the minimum number of clock counts required before the cop timer can be reset in windowed cop mode (copw = 1). cop overflow count copclks copt[1:0] n/a 0:0 n/a n/a cop is disabled 0 0:1 1 khz lpo clock n/a 2 5 cycles (32 ms 2 ) 2 values shown in milliseconds based on t lpo = 1 ms. see t lpo in the appendix section a.12.1, ?control timing ,? for the tolerance of this value. 0 1:0 1 khz lpo clock n/a 2 8 cycles (256 ms 1 ) 0 1:1 1 khz lpo clock n/a 2 10 cycles (1.024 s 1 ) 10 : 1 busclk 6144 cycles 2 13 cycles 11:0 busclk 49,152 cycles 2 16 cycles 11:1 busclk 196,608 cycles 2 18 cycles 76543210 r copclks 1 copw 1 000 spi1fe spi2fe acic w r e s e t00000110 = unimplemented or reserved 1 this bit can be written only one time after reset. additional writes are ignored. figure 5-6. system options register 2 (sopt2) table 5-7. sopt2 register field descriptions field description 7 copclks cop watchdog clock select ? this write-once bit selects the clock source of the cop watchdog. 0 internal 1 khz lpo clock is source to cop. 1 bus clock is source to cop. 6 copw cop window ? this write-once bit selects the cop operatio n mode. when set, the 0x55-0xaa write sequence to the srs register must occur in the last 25% of the se lected period. any write to the srs register during the first 75% of the selected period will reset the mcu. 0 normal cop operation. 1 window cop operation. 2 spi1fe spi1 ports input filter enable 0 disable input filter on spi1 port pins to allow for higher maximum spi baud rate. 1 enable input filter on spi1 port pins to elim inate noise and restrict maximum spi baud rate.
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 73 5.7.6 system device identificati on register (sdidh, sdidl) this read-only register is included, so host development systems can identify the hcs08 derivative and revision number. this allows the development soft ware to recognize where specific memory blocks, registers, and control bits are located in a target mcu. 1 spi2fe spi2 ports input filter enable 0 disable input filter on spi2 port pins to allow for higher maximum spi baud rate. 1 enable input filter on spi2 port pins to elim inate noise and restrict maximum spi baud rate 0 acic analog comparator to input capture enable ? this bit connects the output of acmp to tpm input channel 0. 0 acmp output not connected to tpm input channel 0. 1 acmp output connected to tpm input channel 0. 76543210 r id11 id10 id9 id8 w reset ???? 0000 = unimplemented or reserved figure 5-7. system device identification register ? high (sdidh) table 5-8. sdidh register field descriptions field description 7:4 reserved bits 7:4 are reserved. reading these bi ts will result in an indetermina te value; writes have no effect. 3:0 id[11:8] part identification number ? each derivative in the hcs08 family has a unique identification number. the MC9S08JM16 series is hard coded to the value 0x01e. see also id bits in ta b l e 5 - 9 . 76543210 r id7 id6 id5 id4 id3 id2 id1 id0 w r e s e t00011110 = unimplemented or reserved figure 5-8. system device identification register ? low (sdidl) table 5-9. sdidl register field descriptions field description 7:0 id[7:0] part identification number ? each derivative in the hcs08 family has a unique identification number. the MC9S08JM16 series is hard coded to the value 0x01e. see also id bits in ta b l e 5 - 8 . table 5-7. sopt2 register field descriptions (continued) field description
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 74 freescale semiconductor 5.7.7 system power management st atus and control 1 register (spmsc1) this high page register contains st atus and control bits to support the low-voltage detect function, and to enable the bandgap voltage reference for use by the adc module. this regi ster must be written during the user?s reset initialization pr ogram to set the desired controls even if the desired settings are the same as the reset settings. 76543210 rlvwf 1 0 lv w i e lv d r e 2 lv d s e lv d e 2 0 bgbe w lv wac k r e s e t :00011100 = unimplemented or reserved 1 lvwf will be set in the case when v supply transitions below the trip point or after reset and v supply is already below v lvw . 2 this bit can be written only one time after reset. additional writes are ignored. figure 5-9. system power management status and control 1 register (spmsc1) table 5-10. spmsc1 regist er field descriptions field description 7 lv w f low-voltage warning flag ? the lvwf bit indicates the low-voltage warning status. 0 low-voltage warning is not present. 1 low-voltage warning is present or was present. 6 lv wac k low-voltage warning acknowledge ? if lvwf = 1, a low-voltage condition has occurred. to acknowledge this low-voltage warning, write 1 to lvwack, which will automatically clear lvwf to 0 if the low-voltage warning is no longer present. 5 lv w i e low-voltage warning interrupt enable ? this bit enables hardware interrupt requests for lvwf. 0 hardware interrupt disabled (use polling). 1 request a hardware interrupt when lvwf = 1. 4 lvdre low-voltage detect reset enable ? this write-once bit enables lv d events to generate a hardware reset (provided lvde = 1). 0 lvd events do not generate hardware resets. 1 force an mcu reset when an enabled low-voltage detect event occurs. 3 lv d s e low-voltage detect stop enable ? provided lvde = 1, this read/writ e bit determines whether the low-voltage detect function operates when the mcu is in stop mode. 0 low-voltage detect disabled during stop mode. 1 low-voltage detect enabled during stop mode. 2 lv d e low-voltage detect enable ? this write-once bit enables low-volt age detect logic and qualifies the operation of other bits in this register. 0 lvd logic disabled. 1 lvd logic enabled. 0 bgbe bandgap buffer enable ? this bit enables an internal buffer for the bandgap voltage reference for use by the adc module on one of its internal channels. 0 bandgap buffer disabled. 1 bandgap buffer enabled.
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 75 5.7.8 system power management st atus and control 2 register (spmsc2) this register is used to report the status of the low-voltage warning function, and to configure the stop mode behavior of the mcu. this re gister must be written during the us er?s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. 76543 210 r0 0 lv dv lv w v ppdf 0 0 ppdc 1 w ppdack p o w e r - o n r e s e t :00000 000 l v d r e s e t :00uu0 000 any other reset: 0 0 u u 0 0 0 0 = unimplemented or reserved u = unaffected by reset 1 this bit can be written only one time after reset. additional writes are ignored. figure 5-10. system power management status and control 2 register (spmsc2) table 5-11. spmsc2 regist er field descriptions field description 5 lv dv low-voltage detect voltage select ? this write-once bit selects the low-voltage detect (lvd) trip point setting. it also selects the warning voltage range. see ta bl e 5 - 1 2 . 4 lv w v low-voltage warning voltage select ? this bit selects the low-voltage warning (lvw) trip point voltage.see ta bl e 5 - 1 2 . 3 ppdf partial power down flag ? this read-only status bit indicates that the mcu has recovered from stop2 mode. 0 mcu has not recovered from stop2 mode. 1 mcu recovered from stop2 mode. 2 ppdack partial power down acknowledge ? writing a 1 to ppdack clears the ppdf bit. 0 ppdc partial power down control ? this write-once bit controls whet her stop2 or stop3 mode is selected. 0 stop3 mode enabled. 1 stop2, partial power down, mode enabled. table 5-12. lvd and lvw trip point typical values 1 1 see electrical characteristics appendix for minimum and maximum values. lvdv:lvwv lvw trip point lvd trip point 0:0 v lv w 0 = 2.74 v v lv d 0 = 2.56 v 0:1 v lv w 1 = 2.92 v 1:0 v lv w 2 = 4.3 v v lv d 1 = 4.0 v 1:1 v lv w 3 = 4.6 v
chapter 5 resets, interrupts, and system configuration MC9S08JM16 series data sheet, rev. 2 76 freescale semiconductor
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 77 chapter 6 parallel input/output 6.1 introduction this chapter explains software cont rols related to parallel input/output (i/o). the MC9S08JM16 has seven i/o ports which include a total of 37 general-purpos e i/o pins. see chapter 2, ?pins and connections ,? for more information about the logic a nd hardware aspects of these pins. not all pins are available on all devices. see table 2-1 to determine which func tions are available for a specific device. many of the i/o pins are shared with on- chip peripheral functions, as shown in table 2-1 . the peripheral modules have priority over the i/os, so when a pe ripheral is enabled, the i/o functions are disabled. after reset, the shared peripheral func tions are disabled so th at the pins are controlled by the parallel i/o. all of the parallel i/o are confi gured as inputs (ptxddn = 0). the pin control functions for each pin are configured as follows: slew rate control enabled (p txsen = 1), low drive streng th selected (ptxdsn = 0), and internal pullups di sabled (ptxpen = 0). note not all general-purpose i/o pins are av ailable on all packages. to avoid extra current drain from floating input pins, the user?s reset initialization routine in the application program must either enable on-chip pullup devices or change the direction of unconnected pins to outputs so the pins do not float.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 78 freescale semiconductor 6.2 port data and data direction reading and writing of parallel i/o is done through the port data registers. the direction, input or output, is controlled through the port data di rection registers. the parallel i/ o port function for an individual pin is illustrated in the block diagram below. figure 6-1. parallel i/o block diagram the data direction control bits determine whether the pin output driver is enabled, and they control what is read for port data register read s. each port pin has a data directi on register bit. when ptxddn = 0, the corresponding pin is an input and reads of ptxd return the pin value. when ptxddn = 1, the corresponding pin is an output and read s of ptxd return the last value written to the port data register. when a peripheral module or system function is in control of a port pin, the data direction register bit still controls what is returned for reads of the port da ta register, even though th e peripheral system has overriding control of the actual pin direction. when a shared analog function is enabled for a pin, all digital pin functions are di sabled. a read of the port data register returns a value of 0 for any bits whic h have shared analog functi ons enabled. in general, whenever a pin is shared with both an alternate di gital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. write to the port data register befo re changing the direction of a port pi n to become an output. this ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. q d q d 1 0 port read ptxddn ptxdn output enable output data input data synchronizer data busclk
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 79 6.3 pin control the pin control registers are located in the high page register block of the memory. these registers are used to control pullups, slew rate, a nd drive strength for the i/o pins. the pin control registers operate independently of the pa rallel i/o registers. 6.3.1 internal pullup enable an internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the pullup enable registers (ptxpen). the pullup device is di sabled if the pin is configured as an output by the parallel i/o control logic or any shared peripheral functi on regardless of the state of the corresponding pullup enable register bit. the pull up device is also disabled if the pin is controll ed by an analog function. 6.3.2 output slew rate control enable slew rate control can be enabled for each port pin by setting the corres ponding bit in one of the slew rate control registers (ptxsen). when enab led, slew control limits the rate at which an output can transition in order to reduce emc emissions. slew rate control has no effect on pins which are configured as inputs. 6.3.3 output drive strength select an output pin can be selected to have high output drive strength by setting the corresponding bit in one of the drive strength select registers (p txdsn). when high drive is selected a pin is capable of sourcing and sinking greater current. even though ev ery i/o pin can be selected as high drive, the user must ensure that the total current source a nd sink limits for the chip are not exceed ed. drive strength se lection is intended to affect the dc behavior of i/o pi ns. however, the ac behavior is also affected. high drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. because of this the emc emi ssions may be affected by en abling pins as high drive. 6.4 pin behavior in stop modes depending on the stop mode, i/o functions differently as the result of executing a stop instruction. an explanation of i/o behavior fo r the various stop modes follows: ? stop2 mode is a partial power-down mode, whereby i/o latches are maintained in their state as before the stop instruction was ex ecuted. cpu register status and the state of i/o registers must be saved in ram before the st op instruction is executed to place the mcu in stop2 mode. upon recovery from stop2 mode, before accessing any i/o, the user must examine the state of the ppdf bit in the spmsc2 register. if the ppdf bit is 0, i/o must be initia lized as if a pow er on reset had occurred. if the ppdf bit is 1, i/o data previously stored in ram, before the stop instruction was executed, peripherals may require being initiali zed and restored to their pre-stop condition. the user must then write a 1 to the ppdack bit in th e spmsc2 register. access to i/o is now permitted again in the user?s application program. ? in stop3 mode, all i/o is maintained because internal logic circuity stays powered up. upon recovery, normal i/o function is available to the user.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 80 freescale semiconductor 6.5 parallel i/o and pin control registers this section provides information about the registers associated with the parallel i/o ports and pin control functions. these parallel i/o regist ers are located in page zero of th e memory map and the pin control registers are located in the high pa ge register section of memory. refer to tables in chapter 4, ?memory ,? for the absolute address assign ments for all parallel i/o and pin control registers. this section refe rs to registers and control bits onl y by their names. a freescale-provided equate or header file nor mally is used to translate these names into the appropriate absolute addresses. 6.5.1 port a i/o registers (ptad and ptadd) port a parallel i/o function is cont rolled by the registers listed below. 76543210 r ptad5 ptad0 w reset00000000 figure 6-2. port a data register (ptad) table 6-1. ptad register field descriptions field description 5,0 ptad[5,0] port a data register bits ? for port a pins that are inputs, reads return the logic level on the pin. for port a pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port a pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptad to all 0s, but these 0s are not driven out the corresponding pins be cause reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r ptadd5 ptadd0 w r e s e t00000000 figure 6-3. data direction for port a register (ptadd) table 6-2. ptadd register field descriptions field description 5,0 ptadd[5,0] data direction for port a bits ? these read/write bits control the direction of port a pins and what is read for ptad reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port a bit n and ptad reads return the contents of ptadn.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 81 6.5.2 port a pin control registers (ptape, ptase, ptads) in addition to the i/o control, port a pins are controlled by the registers listed below. 76543210 r ptape5 ptape0 w r e s e t00000000 figure 6-4. internal pullup enable for port a (ptape) table 6-3. ptadd register field descriptions field description 5,0 ptape[5,0] internal pullup enable for port a bits ? each of these control bits determines if the internal pullup device is enabled for the associated pta pin. for port a pins that are configured as outputs, t hese bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port a bit n. 1 internal pullup device enabled for port a bit n. 76543210 r ptase5 ptase0 w r e s e t00111111 figure 6-5. output slew rate control enable for port a (ptase) table 6-4. ptase register field descriptions field description 5,0 ptase[5,0] output slew rate control enable for port a bits ? each of these control bits determine whether output slew rate control is enabled for the associated pta pin. for po rt a pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port a bit n. 1 output slew rate control enabled for port a bit n. 76543210 r ptads5 ptads0 w reset00000000 figure 6-6. output drive strength selection for port a (ptase)
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 82 freescale semiconductor 6.5.3 port b i/o registers (ptbd and ptbdd) port b parallel i/o function is cont rolled by the registers listed below. table 6-5. ptase register field descriptions field description 5,0 ptads[5,0] output drive strength selection for port a bits ? each of these control bits selects between low and high output drive for the associated pta pin. 0 low output drive enabled for port a bit n. 1 high output drive enabled for port a bit n. 76543210 r ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 w reset00000000 figure 6-7. port b data register (ptbd) table 6-6. ptbd regist er field descriptions field description 5:0 ptbd[5:0] port b data register bits ? for port b pins that are inputs, reads return the logic level on the pin. for port b pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port b pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptbd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 w r e s e t00000000 figure 6-8. data direct ion for port b (ptbdd) table 6-7. ptbdd register field descriptions field description 5:0 ptbdd[5:0] data direction for port b bits ? these read/write bits control the direction of port b pins and what is read for ptbd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port b bit n and ptbd reads return the contents of ptbdn.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 83 6.5.4 port b pin control regi sters (ptbpe, ptbse, ptbds) in addition to the i/o control, port b pins are controlled by the registers listed below. 76543210 r ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 w reset00000000 figure 6-9. internal pullup enable for port b (ptbpe) table 6-8. ptbpe register field descriptions field description 5:0 ptbpe[5:0] internal pullup enable for port b bits ? each of these control bits determines if the internal pullup device is enabled for the associated ptb pin. for port b pins that are configured as outputs, thes e bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port b bit n. 1 internal pullup device enabled for port b bit n. 76543210 r ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 w reset00111111 figure 6-10. output slew rate control enable (ptbse) table 6-9. ptbse register field descriptions field description 5:0 ptbse[5:0] output slew rate control enable for port b bits ? each of these control bits determine whether output slew rate control is enabled for the associated ptb pin. for por t b pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port b bit n. 1 output slew rate control enabled for port b bit n.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 84 freescale semiconductor 6.5.5 port c i/o registers (ptcd and ptcdd) port c parallel i/o function is cont rolled by the registers listed below. 76543210 r ptbds5 ptbds4 ptbds3 ptbds2 ptbds1 ptbds0 w reset 00000000 figure 6-11. output drive strength selection for port b (ptbds) table 6-10. ptbds register field descriptions field description 5:0 ptbds[5:0] output drive strength selection for port b bits ? each of these control bits selects between low and high output drive for the associated ptb pin. 0 low output drive enabled for port b bit n. 1 high output drive enabled for port b bit n. 76543210 r ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 w reset00000000 figure 6-12. port c data register (ptcd) table 6-11. ptcd register field descriptions field description 5:0 ptcd[5:0] port c data register bits ? for port c pins that are inputs, reads retu rn the logic level on the pin. for port c pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port c pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptcd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 85 6.5.6 port c pin control regi sters (ptcpe, ptcse, ptcds) in addition to the i/o control, port c pins are controlled by the registers listed below. 76543210 r ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 w reset00000000 figure 6-13. data direction for port c (ptcdd) table 6-12. ptcdd regist er field descriptions field description 5:0 ptcdd[5:0] data direction for port c bits ? these read/write bits control the direction of port c pins and what is read for ptcd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port c bit n and ptcd reads return the contents of ptcdn. 76543210 r ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 w reset00000000 figure 6-14. internal pullup enable for port c (ptcpe) table 6-13. ptcpe register field descriptions field description 5:0 ptcpe[5:0] internal pullup enable for port c bits ? each of these control bits determines if the internal pullup device is enabled for the associated ptc pin. for port c pins that are configured as ou tputs, these bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port c bit n. 1 internal pullup device enabled for port c bit n.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 86 freescale semiconductor 76543210 r ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 w reset00111111 figure 6-15. output slew rate control enable for port c (ptcse) table 6-14. ptcse register field descriptions field description 5:0 ptcse[5:0] output slew rate control enable for port c bits ? each of these control bits determine whether output slew rate control is enabled for the associated ptc pin. for po rt c pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port c bit n. 1 output slew rate control enabled for port c bit n. 76543210 r ptcds5 ptcds4 ptcds3 ptcds2 ptcds1 ptcds0 w r e s e t00000000 figure 6-16. output drive strength selection for port c (ptcds) table 6-15. ptcds register field descriptions field description 5:0 ptcds[5:0] output drive strength selection for port c bits ? each of these control bits selects between low and high output drive for the associated ptc pin. 0 low output drive enabled for port c bit n. 1 high output drive enabled for port c bit n.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 87 6.5.7 port d i/o registers (ptdd and ptddd) port d parallel i/o function is cont rolled by the registers listed below. 76543210 r ptdd7 ptdd2 ptdd1 ptdd0 w reset00000000 figure 6-17. port d data register (ptdd) table 6-16. ptdd register field descriptions field description 7, 2:0 ptdd[7, 2:0] port d data register bits ? for port d pins that are inputs, reads return the logic level on the pin. for port d pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port d pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptdd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r ptddd7 ptddd2 ptddd1 ptddd0 w reset00000000 figure 6-18. data direction for port d (ptddd) table 6-17. ptddd regist er field descriptions field description 7, 2:0 ptddd[7, 2:0] data direction for port d bits ? these read/write bits control the direct ion of port d pins and what is read for ptdd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port d bit n and ptdd reads return the contents of ptddn.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 88 freescale semiconductor 6.5.8 port d pin control regi sters (ptdpe, ptdse, ptdds) in addition to the i/o control, port d pins are controlled by the registers listed below. 76543210 r ptdpe7 ptdpe2 ptdpe1 ptdpe0 w reset00000000 figure 6-19. internal pullup enable for port d (ptdpe) table 6-18. ptdpe register field descriptions field description 7, 2:0 ptdpe[7, 2:0] internal pullup enable for port d bits ? each of these control bits determines if the internal pullup device is enabled for the associated ptd pin. for port d pins that are configured as outputs, thes e bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port d bit n. 1 internal pullup device enabled for port d bit n. 76543210 r ptdse7 ptdse2 ptdse1 ptdse0 w reset11111111 figure 6-20. output slew rate control enable for port d (ptdse) table 6-19. ptdse register field descriptions field description 7, 2:0 ptdse[7, 2:0] output slew rate control enable for port d bits ? each of these control bits determine whether output slew rate control is enabled for the associated ptd pin. for port d pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port d bit n. 1 output slew rate control enabled for port d bit n.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 89 6.5.9 port e i/o registers (pted and ptedd) port e parallel i/o function is cont rolled by the registers listed below. 76543210 r ptdds7 ptdds2 ptdds1 ptdds0 w r e s e t00000000 figure 6-21. output drive strength selection for port d (ptdds) table 6-20. ptdds regi ster field descriptions field description 7, 2:0 ptdds[7, 2:0] output drive strength selection for port d bits ? each of these control bits selects between low and high output drive for the associated ptd pin. 0 low output drive enabled for port d bit n. 1 high output drive enabled for port d bit n. 76543210 r pted7 pted6 pted5 pted4 pted3 pted2 pted1 pted0 w r e s e t00000000 figure 6-22. port e data register (pted) table 6-21. pted register field descriptions field description 7:0 pted[7:0] port e data register bits ? for port e pins that are inputs, reads return the logic level on the pin. for port e pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port e pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces pted to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 90 freescale semiconductor 76543210 r ptedd7 ptedd6 ptedd5 ptedd4 ptedd3 ptedd2 ptedd1 ptedd0 w r e s e t00000000 figure 6-23. data direction for port e (ptedd) table 6-22. ptedd register field descriptions field description 7:0 ptedd[7:0] data direction for port e bits ? these read/write bits control the direction of port e pins and what is read for pted reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port e bit n and pted reads return the contents of ptedn.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 91 6.5.10 port e pin control regi sters (ptepe, ptese, pteds) in addition to the i/o control, port e pins are controlled by the registers listed below. 76543210 r ptepe7 ptepe6 ptepe5 ptepe4 ptepe3 ptepe2 ptepe1 ptepe0 w r e s e t00000000 figure 6-24. internal pullup enable for port e (ptepe) table 6-23. ptepe register field descriptions field description 7:0 ptepe[7:0] internal pullup enable for port e bits ? each of these control bits determines if the internal pullup device is enabled for the associated pte pin. for port e pins that are configured as outputs, thes e bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port e bit n. 1 internal pullup device enabled for port e bit n. 76543210 r ptese7 ptese6 ptese5 ptese4 ptese3 ptese2 ptese1 ptese0 w r e s e t11111111 figure 6-25. output slew rate control enable for port e (ptese) table 6-24. ptese register field descriptions field description 7:0 ptese[7:0] output slew rate control enable for port e bits ? each of these control bits determine whether output slew rate control is enabled for the associated pte pin. for por t e pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port e bit n. 1 output slew rate control enabled for port e bit n.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 92 freescale semiconductor 6.5.11 port f i/o registers (ptfd and ptfdd) port f parallel i/o function is cont rolled by the registers listed below. 76543210 r pteds7 pteds6 pteds5 pteds4 pteds3 pteds2 pteds1 pteds0 w reset00000000 figure 6-26. output drive strength selection for port e (pteds) table 6-25. pteds register field descriptions field description 7:0 pteds[7:0] output drive strength selection for port e bits ? each of these control bits selects between low and high output drive for the associated pte pin. 0 low output drive enabled for port e bit n. 1 high output drive enabled for port e bit n. 76543210 r ptfd6 ptfd5 ptfd4 ptfd1 ptfd0 w reset00000000 figure 6-27. port f data register (ptfd) table 6-26. ptfd register field descriptions field description 6:4, 1:0 ptfd [6:4, 1:0] port f data register bits ? for port f pins that are inputs, reads return the logic level on the pin. for port f pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port f pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptfd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 93 6.5.12 port f pin control registers (ptfpe, ptfse, ptfds) in addition to the i/o control, port f pins are controlled by the registers listed below. 76543210 r ptfdd6 ptfdd5 ptfdd4 ptfdd1 ptfdd0 w r e s e t00000000 figure 6-28. data direction for port f (ptfdd) table 6-27. ptfdd register field descriptions field description 6:4, 1:0 ptfdd [6:4, 1:0] data direction for port f bits ? these read/write bits control the directio n of port f pins and what is read for ptfd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port f bit n and ptfd reads return the contents of ptfdn. 76543210 r ptfpe6 ptfpe5 ptfpe4 ptfpe1 ptfpe0 w reset00000000 figure 6-29. internal pullup enable for port f (ptfpe) table 6-28. ptfpe register field descriptions field description 6:4, 1:0 ptfpe [6:4, 1:0] internal pullup enable for port f bits ? each of these control bits determi nes if the internal pullup device is enabled for the associated ptf pin. for port f pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port f bit n. 1 internal pullup device enabled for port f bit n.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 94 freescale semiconductor 76543210 r ptfse6 ptfse5 ptfse4 ptfse1 ptfse0 w reset01111111 figure 6-30. output slew rate control enable for port f (ptfse) table 6-29. ptfse register field descriptions field description 6:4, 1:0 ptfse [6:4, 1:0] output slew rate control enable for port f bits ? each of these control bits determine whether output slew rate control is enabled for the associated ptf pin. for port f pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port f bit n. 1 output slew rate control enabled for port f bit n. 76543210 r ptfds6 ptfds5 ptfds4 ptfds1 ptfds0 w reset00000000 figure 6-31. output drive strength selection for port f (ptfds) table 6-30. ptfds register field descriptions field description 6:4, 1:0 ptfds [6:4, 1:0] output drive strength selection for port f bits ? each of these control bits selects between low and high output drive for the associated ptf pin. 0 low output drive enabled for port f bit n. 1 high output drive enabled for port f bit n.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 95 6.5.13 port g i/o registers (ptgd and ptgdd) port g parallel i/o function is cont rolled by the registers listed below. 76543210 r ptgd5 ptgd4 ptgd3 ptgd2 ptgd1 ptgd0 w reset00000000 figure 6-32. port g data register (ptgd) table 6-31. ptgd register field descriptions field description 5:0 ptgd[5:0] port g data register bits ? for port g pins that are inputs, reads return the logic level on the pin. for port g pins that are configured as outputs, reads retu rn the last value written to this register. writes are latched into all bits of this register. for port g pins that are configured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptgd to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 76543210 r ptgdd5 ptgdd4 ptgdd3 ptgdd2 ptgdd1 ptgdd0 w r e s e t00000000 figure 6-33. data direction for port g (ptgdd) table 6-32. ptgdd register field descriptions field description 5:0 ptgdd[5:0] data direction for port g bits ? these read/write bits control the directio n of port g pins and what is read for ptgd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port g bit n and ptgd reads return the contents of ptgdn.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 96 freescale semiconductor 6.5.14 port g pin control regi sters (ptgpe, ptgse, ptgds) in addition to the i/o control, port g pins are controlled by the registers listed below. 76543210 r ptgpe5 ptgpe4 ptgpe3 ptgpe2 ptgpe1 ptgpe0 w r e s e t00000000 figure 6-34. internal pullup enable for port g bits (ptgpe) table 6-33. ptgpe register field descriptions field description 5:0 ptgpen internal pullup enable for port g bits ? each of these control bits determines if the internal pullup device is enabled for the associated ptg pin. for port g pins that ar e configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 internal pullup device disabled for port g bit n. 1 internal pullup device enabled for port g bit n. 76543210 r ptgse5 ptgse4 ptgse3 ptgse2 ptgse1 ptgse0 w r e s e t00111111 figure 6-35. output slew rate control enable for port g bits (ptgse) table 6-34. ptgse register field descriptions field description 5:0 ptgsen output slew rate control enable for port g bits ? each of these control bits determine whether output slew rate control is enabled for the associated ptg pin. for port g pins that are configured as inputs, these bits have no effect. 0 output slew rate control disabled for port g bit n. 1 output slew rate control enabled for port g bit n.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 97 76543210 r ptgds5 ptgds4 ptgds3 ptgds2 ptgds1 ptgds0 w r e s e t00000000 figure 6-36. output drive strengt h selection for port g (ptgds) table 6-35. ptgds register field descriptions field description 5:0 ptgdsn output drive strength selection for port g bits ? each of these control bits selects between low and high output drive for the associated ptg pin. 0 low output drive enabled for port g bit n. 1 high output drive enabled for port g bit n.
chapter 6 parallel input/output MC9S08JM16 series data sheet, rev. 2 98 freescale semiconductor
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 99 chapter 7 central processor unit (s08cpuv2) 7.1 introduction this section provides summary information about the re gisters, addressing modes, and instruction set of the cpu of the hcs08 family. for a more detailed discussion, refer to the hcs08 family reference manual, volume 1, freescale semiconductor documen t order number hcs08rmv1/d. the hcs08 cpu is fully source- and object-code -compatible with the m68hc08 cpu. several instructions and enhanced addressi ng modes were added to improve c compiler efficiency and to support a new background debug system which replaces the m onitor mode of earlier m68hc08 microcontrollers (mcu). 7.1.1 features features of the hcs08 cpu include: ? object code fully upward-compatible with m68hc05 a nd m68hc08 families ? all registers and memory are mappe d to a single 64-kbyte address space ? 16-bit stack pointer (any size stack anywhere in 64-kbyte address space) ? 16-bit index register (h:x) with powerful indexed addressing modes ? 8-bit accumulator (a) ? many instructions treat x as a second general-purpose 8-bit register ? seven addressing modes: ? inherent ? operands in internal registers ? relative ? 8-bit signed offs et to branch destination ? immediate ? operand in next object code byte(s) ? direct ? operand in memory at 0x0000?0x00ff ? extended ? operand anywhere in 64-kbyte address space ? indexed relative to h:x ? five submodes including auto increment ? indexed relative to sp ? impr oves c efficiency dramatically ? memory-to-memory data move instructions with four address mode combinations ? overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (bcd) operations ? efficient bit manipulation instructions ? fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions ? stop and wait instructions to invoke low-power operating modes
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 100 freescale semiconductor 7.2 programmer?s model and cpu registers figure 7-1 shows the five cpu registers. cpu regi sters are not part of the memory map. figure 7-1. cpu registers 7.2.1 accumulator (a) the a accumulator is a general-purpose 8-bit regist er. one operand input to the arithmetic logic unit (alu) is connected to the accumulator and the alu re sults are often stored into the a accumulator after arithmetic and logical ope rations. the accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data co mes from, or the contents of a can be stored to memory using various addressing m odes to specify the address where data from a will be stored. reset has no effect on the c ontents of the a accumulator. 7.2.2 index register (h:x) this 16-bit register is actually two separate 8-bit regist ers (h and x), which often work together as a 16-bit address pointer where h holds the upp er byte of an address and x holds the lower byte of the address. all indexed addressing mode instructions use the full 16-bit value in h:x as an index reference pointer; however, for compatibility with the earlier m68hc 05 family, some instructions operate only on the low-order 8-bit half (x). many instructions treat x as a second general-purpose 8- bit register that can be used to hold 8-bit data values. x can be cleared, incremented, decremented, co mplemented, negated, shifted, or rotated. transfer instructions allow data to be transferred from a or tr ansferred to a where arithm etic and logical operations can then be performed. for compatibility with the earlier m68hc05 family, h is fo rced to 0x00 during reset. reset has no effect on the contents of x. sp pc condition code register carry zero negative interrupt mask half-carry (from bit 3) two?s complement overflow h x 0 0 0 7 15 15 70 accumulator a index register (low) index register (high) stack pointer 87 program counter 16-bit index register h:x ccr c v11hinz
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 101 7.2.3 stack pointer (sp) this 16-bit address pointer register points at the next available locati on on the automatic last-in-first-out (lifo) stack. the stack may be lo cated anywhere in the 64-kbyte a ddress space that has ram and can be any size up to the amount of available ram. the stac k is used to automaticall y save the return address for subroutine calls, the return address and cpu regi sters during interrupts, and for local variables. the ais (add immediate to stack pointer) instruction adds an 8-bit signed immediate valu e to sp. this is most often used to allocate or deallocate space for local variables on the stack. sp is forced to 0x00ff at reset for compatibility with the earlier m68hc 05 family. hcs08 programs normally change the value in sp to the address of the last location (highest address) in on-chip ram during reset initialization to free up direct page ra m (from the end of the on-chip registers to 0x00ff). the rsp (reset stack pointer) instruction was includ ed for compatibility with the m68hc05 family and is seldom used in new hcs08 progr ams because it only affects the low- order half of the stack pointer. 7.2.4 program counter (pc) the program counter is a 16-bit register that contai ns the address of the next instruction or operand to be fetched. during normal program execution, the program counter automatically increments to the next sequential memory location every time an in struction or operand is fetched. ju mp, branch, interrupt, and return operations load the program counter with an address ot her than that of the next sequential location. this is called a change-of-flow. during reset, the program counter is loaded with the reset vector that is located at 0xfffe and 0xffff. the vector stored there is the address of the first in struction that will be execu ted after exiting the reset state. 7.2.5 condition code register (ccr) the 8-bit condition code register contai ns the interrupt mask (i) and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set pe rmanently to 1. the following paragraphs describe the functions of the condition code bits in general term s. for a more detailed explanation of how each instruction sets the ccr bits, refer to the hcs08 family reference manual, volume 1, freescale semiconductor document order number hcs08rmv1.
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 102 freescale semiconductor figure 7-2. condition code register table 7-1. ccr register field descriptions field description 7 v two?s complement overflow flag ? the cpu sets the overflow flag when a two?s complement overflow occurs. the signed branch instructions bgt, bg e, ble, and blt use the overflow flag. 0 no overflow 1overflow 4 h half-carry flag ? the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operati on. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction us es the states of the h and c condition code bits to automatically add a correction value to the result from a previous add or adc on bcd operands to correct the result to a valid bcd value. 0 no carry between bits 3 and 4 1 carry between bits 3 and 4 3 i interrupt mask bit ? when the interrupt mask is set, all maska ble cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers ar e saved on the stack, but before the firs t instruction of the interrupt service routine is executed. interrupts are not recognized at the inst ruction boundary after any instruction that clears i (cli or tap). this ensures that the next instru ction after a cli or tap will always be execut ed without the possibility of an intervening interrupt, provided i was set. 0 interrupts enabled 1 interrupts disabled 2 n negative flag ? the cpu sets the negative flag when an arithmetic operation, logi c operation, or data manipulation produces a negative result, setting bit 7 of the result. simply loading or storing an 8-bit or 16-bit value causes n to be set if the most significant bit of the loaded or stored value was 1. 0 non-negative result 1 negative result 1 z zero flag ? the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of 0x00 or 0x0000. simply loading or storing an 8-bit or 16-bit value causes z to be set if the loaded or stored value was all 0s. 0 non-zero result 1zero result 0 c carry/borrow flag ? the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation require s a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 0 no carry out of bit 7 1 carry out of bit 7 condition code register carry zero negative interrupt mask half-carry (from bit 3) two?s complement overflow 70 ccr c v11hinz
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 103 7.3 addressing modes addressing modes define the way th e cpu accesses operands and data. in the hcs08, all memory, status and control registers, and input/out put (i/o) ports share a single 64-kbyt e linear address space so a 16-bit binary address can uniquely identify any memory location. this arrangement means that the same instructions that access va riables in ram can also be used to acce ss i/o and control registers or nonvolatile program space. some instructions use more than one addressing mode. for instance, m ove instructions use one addressing mode to specify the source operand and a second addressing mode to specify the destination address. instructions such as brclr, brset, cbeq, and db nz use one addressing mode to specify the location of an operand for a test and then use relative addres sing mode to specify the branch destination address when the tested condition is true . for brclr, brset, cbeq, and dbnz , the addressing mode listed in the instruction set tables is the addressing mode need ed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 7.3.1 inherent addressing mode (inh) in this addressing mode, operands needed to complete the instruction (if any) are located within cpu registers so the cpu does not need to access memory to get any operands. 7.3.2 relative addressing mode (rel) relative addressing mode is used to specify the destination locatio n for branch instructions. a signed 8-bit offset value is located in the memory location immediate ly following the opcode. during execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 7.3.3 immediate addressing mode (imm) in immediate addressing mode, the op erand needed to complete the inst ruction is included in the object code immediately followi ng the instruction opcode in memory. in the case of a 16-bi t immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memo ry location after that. 7.3.4 direct addressing mode (dir) in direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x0000?0x00ff). during execution a 16-bit address is formed by concatenati ng an implied 0x00 for the high-order half of the address and th e direct address from the instruction to get the 16-bit address where the desired operand is located. this is faster and more memory efficien t than specifying a complete 16-bit address for the operand.
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 104 freescale semiconductor 7.3.5 extended addressing mode (ext) in extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.3.6 indexed addressing mode indexed addressing mode has seven variations including five that use the 16-bit h:x index register pair and two that use the stack po inter as the base reference. 7.3.6.1 indexed, no offset (ix) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. 7.3.6.2 indexed, no offset with post increment (ix+) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is only used for mov and cbeq instructions. 7.3.6.3 indexed, 8-bit offset (ix1) this variation of indexed addressing uses the 16- bit value in the h:x index regi ster pair plus an unsigned 8-bit offset included in the instruction as the addres s of the operand needed to complete the instruction. 7.3.6.4 indexed, 8-bit offset with post increment (ix1+) this variation of indexed addressing uses the 16- bit value in the h:x index regi ster pair plus an unsigned 8-bit offset included in the instruction as the addres s of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is used only for the cbeq instruction. 7.3.6.5 indexed, 16-bit offset (ix2) this variation of indexed a ddressing uses the 16-bit value in the h:x index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.6 sp-relative, 8-bit offset (sp1) this variation of indexed addressing uses the 16-bit va lue in the stack pointer (sp) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 105 7.3.6.7 sp-relative, 16-bit offset (sp2) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 special operations the cpu performs a few special opera tions that are similar to instruct ions but do not have opcodes like other cpu instructions. in addition, a few instructions such as stop a nd wait directly affect other mcu circuitry. this section provides additional informat ion about these operations. 7.4.1 reset sequence reset can be caused by a power-on-reset (por) event, internal conditions such as the cop (computer operating properly) watchdog, or by assertion of an external active-low reset pin. when a reset event occurs, the cpu immediately stops whatever it is doing (the mcu does not wait for an instruction boundary before responding to a reset event). for a more detailed discussion about how the mcu recognizes resets and determin es the source, refer to the resets, interrupts, and system configuration chapter. the reset event is considered conc luded when the sequence to determin e whether the reset came from an internal source is done and when the reset pin is no longer asse rted. at the conclusion of a reset event, the cpu performs a 6-cycle sequence to fetch the reset vector from 0x fffe and 0xffff and to fill the instruction queue in preparation for execution of the first program instruction. 7.4.2 interrupt sequence when an interrupt is requested, the cpu completes the current instruction before responding to the interrupt. at this point, the program counter is pointing at the start of the next instruction, which is where the cpu must return after servicing the interrupt. the cpu responds to an interrupt by performing the same sequence of operations as for a software interrupt (swi) instruction, except the address used for the vector fetch is determined by the highest priority in terrupt that is pending when the interrupt sequence started. the cpu sequence for an interrupt is: 1. store the contents of pcl, pch, x, a, and ccr on the stack, in that order. 2. set the i bit in the ccr. 3. fetch the high-order half of the interrupt vector. 4. fetch the low-order half of the interrupt vector. 5. delay for one free bus cycle. 6. fetch three bytes of program info rmation starting at the address i ndicated by the interrupt vector to fill the instruction queue in preparation for ex ecution of the first instruction in the interrupt service routine. after the ccr contents are pushed onto the stack, the i bit in the ccr is set to prevent other interrupts while in the interrupt service routin e. although it is possible to clear th e i bit with an instruction in the
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 106 freescale semiconductor interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are di fficult to debug and maintain). for compatibility with the earlier m68hc05 mcus, the hi gh-order half of the h:x index register pair (h) is not saved on the stack as part of the interrupt se quence. the user must use a pshh instruction at the beginning of the service routine to save h and then use a pulh instruction just before the rti that ends the interrupt service routine. it is not necessary to save h if you are certa in that the interr upt service routine does not use any instructions or auto-increment addressing modes that might change the value of h. the software interrupt (swi) instruction is like a ha rdware interrupt except that it is not masked by the global i bit in the ccr and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 7.4.3 wait mode operation the wait instruction enables interrupts by clearing the i bit in the ccr. it then halts the clocks to the cpu to reduce overall power consumpt ion while the cpu is waiting for the interrupt or reset event that will wake the cpu from wait mode. when an interrupt or reset event oc curs, the cpu clocks will resume and the interrupt or reset even t will be processed normally. if a serial background comma nd is issued to the mcu through the background debug interface while the cpu is in wait mode, cpu cloc ks will resume and th e cpu will enter activ e background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu ev en if it is in wait mode. 7.4.4 stop mode operation usually, all system clocks, includi ng the crystal oscillator (when used ), are halted during stop mode to minimize power consumption. in such systems, external circui try is needed to control the time spent in stop mode and to issue a signal to wake up the target mcu when it is time to resume processing. unlike the earlier m68hc05 and m68hc08 mcus, the hcs08 can be configured to keep a minimum set of clocks running in stop mode. this optionally allows an internal periodi c signal to wake the target mcu from stop mode. when a host debug system is connected to the background debug pin (bkgd) and the enbdm control bit has been set by a serial command through the background interface (or because the mcu was reset into active background mode), the oscillator is forced to remain active when the mcu enters stop mode. in this case, if a serial back ground command is issued to the mc u through the background debug interface while the cpu is in stop mode, cpu clocks will resume and the cpu will enter active background mode where other serial backgr ound commands can be processed. this ensures that a host development system can still gain access to a target mcu even if it is in stop mode. recovery from stop mode de pends on the particular hcs08 and whether the osc illator was stopped in stop mode. refer to the modes of operation chapter for more details.
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 107 7.4.5 bgnd instruction the bgnd instruction is new to the hcs08 compar ed to the m68hc08. bgnd would not be used in normal user programs because it forces the cpu to st op processing user instructions and enter the active background mode. the only way to re sume execution of the user program is through reset or by a host debug system issuing a go, trace1, or taggo serial command through the background debug interface. software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the bgnd opcode. when the program re aches this breakpoint address, the cpu is forced to active background mode rather than continuing the user program.
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 108 freescale semiconductor 7.5 hcs08 instruction set summary table 7-2 provides a summary of the hcs08 instruction se t in all possible addressing modes. the table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode vari ation of each instruction. table 7-2. . instruction set summary (sheet 1 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr vh i n z c adc # opr8i adc opr8a adc opr16a adc oprx16,x adc oprx8 ,x adc ,x adc oprx16,sp adc oprx8 ,sp add with carry a (a) + (m) + (c) imm dir ext ix2 ix1 ix sp2 sp1 a9 b9 c9 d9 e9 f9 9e d9 9e e9 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? add # opr8i add opr8a add opr16a add oprx16,x add oprx8 ,x add ,x add oprx16,sp add oprx8 ,sp add without carry a (a) + (m) imm dir ext ix2 ix1 ix sp2 sp1 ab bb cb db eb fb 9e db 9e eb ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? ais # opr8i add immediate value (signed) to stack pointer sp (sp) + (m) imm a7 ii 2 pp ? ? ? ? ? ? aix # opr8i add immediate value (signed) to index register (h:x) h:x (h:x) + (m) imm af ii 2 pp ? ? ? ? ? ? and # opr8i and opr8a and opr16a and oprx16,x and oprx8 ,x and ,x and oprx16,sp and oprx8 ,sp logical and a (a) & (m) imm dir ext ix2 ix1 ix sp2 sp1 a4 b4 c4 d4 e4 f4 9e d4 9e e4 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 ? ? ? asl opr8a asla aslx asl oprx8 ,x asl ,x asl oprx8 ,sp arithmetic shift left (same as lsl) di r inh inh ix1 ix sp1 38 48 58 68 78 9e 68 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ?? asr opr8a asra asrx asr oprx8 ,x asr ,x asr oprx8 ,sp arithmetic shift right dir inh inh ix1 ix sp1 37 47 57 67 77 9e 67 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ?? bcc rel branch if carry bit clear (if c = 0) rel 24 rr 3 ppp ? ? ? ? ? ? c b0 b7 0 b0 b7 c
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 109 bclr n,opr8a clear bit n in memory (mn 0) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp ? ? ? ? ? ? bcs rel branch if carry bit set (if c = 1) (same as blo) rel 25 rr 3 ppp ? ? ? ? ? ? beq rel branch if equal (if z = 1) rel 27 rr 3 ppp ? ? ? ? ? ? bge rel branch if greater than or equal to (if n v = 0) (signed) rel 90 rr 3 ppp ? ? ? ? ? ? bgnd enter active background if enbdm=1 waits for and processes bdm commands until go, trace1, or taggo inh 82 5+ fp...ppp ? ? ? ? ? ? bgt rel branch if greater than (if z | (n v) = 0) (signed) rel 92 rr 3 ppp ? ? ? ? ? ? bhcc rel branch if half carry bit clear (if h = 0) rel 28 rr 3 ppp ? ? ? ? ? ? bhc s rel branch if half carry bit set (if h = 1) rel 29 rr 3 ppp ? ? ? ? ? ? bhi rel branch if higher (if c | z = 0) rel 22 rr 3 ppp ? ? ? ? ? ? bhs rel branch if higher or same (if c = 0) (same as bcc) rel 24 rr 3 ppp ? ? ? ? ? ? bih rel branch if irq pin high (if irq pin = 1) rel 2f rr 3 ppp ? ? ? ? ? ? bil rel branch if irq pin low (if irq pin = 0) rel 2e rr 3 ppp ? ? ? ? ? ? bit # opr8i bit opr8a bit opr16a bit oprx16,x bit oprx8 ,x bit ,x bit oprx16,sp bit oprx8 ,sp bit test (a) & (m) (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a5 b5 c5 d5 e5 f5 9e d5 9e e5 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 ? ? ? ble rel branch if less than or equal to (if z | (n v) = 1) (signed) re l 93 rr 3 ppp ? ? ? ? ? ? blo rel branch if lower (if c = 1) (same as bcs) rel 25 rr 3 ppp ? ? ? ? ? ? bls rel branch if lower or same (if c | z = 1) rel 23 rr 3 ppp ? ? ? ? ? ? blt rel branch if less than (if n v = 1) (signed) rel 91 rr 3 ppp ? ? ? ? ? ? bmc rel branch if interrupt mask clear (if i = 0) rel 2c rr 3 ppp ? ? ? ? ? ? bmi rel branch if minus (if n = 1) rel 2b rr 3 ppp ? ? ? ? ? ? bms rel branch if interrupt mask set (if i = 1) rel 2d rr 3 ppp ? ? ? ? ? ? bne rel branch if not equal (if z = 0) rel 26 rr 3 ppp ? ? ? ? ? ? bpl rel branch if plus (if n = 0) rel 2a rr 3 ppp ? ? ? ? ? ? table 7-2. . instruction set summary (sheet 2 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr vh i n z c
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 110 freescale semiconductor bra rel branch always (if i = 1) rel 20 rr 3 ppp ? ? ? ? ? ? brclr n,opr8a,rel branch if bit n in memory clear (if (mn) = 0) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp ? ? ? ? ? brn rel branch never (if i = 0) rel 21 rr 3 ppp ? ? ? ? ? ? brset n,opr8a ,rel branch if bit n in memory set (if (mn) = 1) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp ? ? ? ? ? bset n,opr8a set bit n in memory (mn 1) di r (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp ? ? ? ? ? ? bsr rel branch to subroutine pc (pc) + $0002 push (pcl); sp (sp) ? $0001 push (pch); sp (sp) ? $0001 pc (pc) + rel rel ad rr 5 ssppp ? ? ? ? ? ? cbeq opr8a ,rel cbeqa # opr8i ,rel cbeqx # opr8i ,rel cbeq oprx8 ,x+, rel cbeq ,x+, rel cbeq oprx8 ,sp, rel compare and... branch if (a) = (m) branch if (a) = (m) branch if (x) = (m) branch if (a) = (m) branch if (a) = (m) branch if (a) = (m) dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e 61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 5 6 rpppp pppp pppp rpppp rfppp prpppp ? ? ? ? ? ? clc clear carry bit (c 0) inh 98 1 p ? ? ? ? ? 0 cli clear interrupt mask bit (i 0) inh 9a 1 p ? ? 0 ? ? ? clr opr8a clra clrx clrh clr oprx8 ,x clr ,x clr oprx8 ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e 6f dd ff ff 5 1 1 1 5 4 6 rfwpp p p p rfwpp rfwp prfwpp 0 ? ? 0 1 ? table 7-2. . instruction set summary (sheet 3 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr vh i n z c
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 111 cmp # opr8i cmp opr8a cmp opr16a cmp oprx16 ,x cmp oprx8 ,x cmp ,x cmp oprx16 ,sp cmp oprx8 ,sp compare accumulator with memory a ? m (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a1 b1 c1 d1 e1 f1 9e d1 9e e1 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ?? com opr8a coma comx com oprx8 ,x com ,x com oprx8 ,sp complement m (m )= $ff ? (m) (one?s complement) a (a ) = $ff ? (a) x (x ) = $ff ? (x) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) dir inh inh ix1 ix sp1 33 43 53 63 73 9e 63 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 0 ? ? 1 cphx opr16a cphx # opr16i cphx opr8a cphx oprx8 ,sp compare index register (h:x) with memory (h:x) ? (m:m + $0001) (ccr updated but operands not changed) ext imm dir sp1 3e 65 75 9e f3 hh ll jj kk dd ff 6 3 5 6 prrfpp ppp rrfpp prrfpp ?? cpx # opr8i cpx opr8a cpx opr16a cpx oprx16 ,x cpx oprx8 ,x cpx ,x cpx oprx16 ,sp cpx oprx8 ,sp compare x (index register low) with memory x ? m (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a3 b3 c3 d3 e3 f3 9e d3 9e e3 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ?? daa decimal adjust accumulator after add or adc of bcd values inh 72 1 p u ? ? dbnz opr8a,rel dbnza rel dbnzx rel dbnz oprx8 ,x, rel dbnz ,x, rel dbnz oprx8 ,sp, rel decrement a, x, or m and branch if not zero (if (result) 0) dbnzx affects x not h dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e 6b dd rr rr rr ff rr rr ff rr 7 4 4 7 6 8 rfwpppp fppp fppp rfwpppp rfwppp prfwpppp ? ? ? ? ? ? dec opr8a deca decx dec oprx8 ,x dec ,x dec oprx8 ,sp decrement m (m) ? $01 a (a) ? $01 x (x) ? $01 m (m) ? $01 m (m) ? $01 m (m) ? $01 dir inh in h ix1 ix sp1 3a 4a 5a 6a 7a 9e 6a dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ?? ? div divide a (h:a) (x); h remainder inh 52 6 fffffp ? ? ? ? eor # opr8i eor opr8a eor opr16a eor oprx16 ,x eor oprx8 ,x eor ,x eor oprx16 ,sp eor oprx8 ,sp exclusive or memory with accumulator a (a m) imm dir ext ix2 ix1 ix sp2 sp1 a8 b8 c8 d8 e8 f8 9e d8 9e e8 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 ? ? ? table 7-2. . instruction set summary (sheet 4 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr vh i n z c
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 112 freescale semiconductor inc opr8a inca incx inc oprx8 ,x inc ,x inc oprx8 ,sp increment m (m) + $01 a (a) + $01 x (x) + $01 m (m) + $01 m (m) + $01 m (m) + $01 dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e 6c dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ?? ? jmp opr8a jmp opr16a jmp oprx16,x jmp oprx8 ,x jmp ,x jump pc jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 3 4 4 3 3 ppp pppp pppp ppp ppp ? ? ? ? ? ? jsr opr8a jsr opr16a jsr oprx16 ,x jsr oprx8 ,x jsr ,x jump to subroutine pc (pc ) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? $0001 push (pch); sp (sp) ? $0001 pc unconditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 6 5 5 ssppp pssppp pssppp ssppp ssppp ? ? ? ? ? ? lda # opr8i lda opr8a lda opr16a lda oprx16,x lda oprx8 ,x lda ,x lda oprx16,sp lda oprx8 ,sp load accumulator from memory a (m) imm dir ext ix2 ix1 ix sp2 sp1 a6 b6 c6 d6 e6 f6 9e d6 9e e6 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 ? ? ? ldhx # opr16i ldhx opr8a ldhx opr16a ldhx ,x ldhx oprx16,x ldhx oprx8 ,x ldhx oprx8 ,sp lo ad index register (h:x) h:x ( m:m + $0001 ) imm dir ext ix ix2 ix1 sp1 45 55 32 9e ae 9e be 9e ce 9e fe jj kk dd hh ll ee ff ff ff 3 4 5 5 6 5 5 ppp rrpp prrpp prrfp pprrpp prrpp prrpp 0 ? ? ? ldx # opr8i ldx opr8a ldx opr16a ldx oprx16,x ldx oprx8 ,x ldx ,x ldx oprx16,sp ldx oprx8 ,sp load x (index register low) from memory x (m) imm dir ext ix2 ix1 ix sp2 sp1 ae be ce de ee fe 9e de 9e ee ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 ? ? ? lsl opr8a lsla lslx lsl op rx8 ,x lsl ,x lsl oprx8 ,sp logical shift left (same as asl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e 68 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ?? lsr opr8a lsra lsr x lsr oprx8 ,x lsr ,x lsr oprx8 ,sp logical shift right dir inh inh ix1 ix sp1 34 44 54 64 74 9e 64 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ?? 0 table 7-2. . instruction set summary (sheet 5 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr vh i n z c c b0 b7 0 b0 b7 c 0
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 113 mov opr8a ,opr8a mov opr8a,x+ mov #opr8i , opr8a mov ,x+, opr8a move (m) destination (m) source in ix+/dir and dir/ix+ modes, h:x (h:x) + $0001 dir/dir dir/ix+ imm/dir ix+/dir 4e 5e 6e 7e dd dd dd ii dd dd 5 5 4 5 rpwpp rfwpp pwpp rfwpp 0 ? ? ? mul unsigned multiply x:a (x) (a) inh 42 5 ffffp ? 0? ? ? 0 neg opr8a nega negx neg oprx8 ,x neg ,x neg oprx8 ,sp negate m ? (m) = $00 ? (m) (two?s complement) a ? (a) = $00 ? (a) x ? (x) = $00 ? (x) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) dir inh inh ix1 ix sp1 30 40 50 60 70 9e 60 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ?? nop no operation ? uses 1 bus cycle inh 9d 1 p ? ? ? ? ? ? nsa n ibble swap accumulator a (a[3:0]:a[7:4]) inh 62 1 p ? ? ? ? ? ? ora # opr8i ora opr8a ora opr16a ora oprx16 ,x ora oprx8 ,x ora ,x ora oprx16 ,sp ora oprx8 ,sp inclusive or accumulator and memory a (a) | (m) imm dir ext ix2 ix1 ix sp2 sp1 aa ba ca da ea fa 9e da 9e ea ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 ? ? ? psha push accumulator onto stack push (a); sp (sp) ? $0001 inh 87 2 sp ? ? ? ? ? ? pshh push h (index register high) onto stack push (h); sp (sp) ? $0001 inh 8b 2 sp ? ? ? ? ? ? pshx push x (index register low) onto stack push (x); sp (sp) ? $0001 inh 89 2 sp ? ? ? ? ? ? pula pull accumulator from stack sp (sp + $0001); pull ( a ) inh 86 3 ufp ? ? ? ? ? ? pulh pull h (index register high) from stack sp (sp + $0001); pull ( h) inh 8a 3 ufp ? ? ? ? ? ? pulx pull x (index register low) from stack sp (sp + $0001); pull ( x ) inh 88 3 ufp ? ? ? ? ? ? rol opr8a rola rolx rol oprx8 ,x rol ,x rol oprx8 ,sp rotate left through carry dir inh inh ix1 ix sp1 39 49 59 69 79 9e 69 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ?? ror opr8a rora rorx ror oprx8 ,x ror ,x ror oprx8 ,sp rotate right through carry dir inh inh ix1 ix sp1 36 46 56 66 76 9e 66 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ?? table 7-2. . instruction set summary (sheet 6 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr vh i n z c c b0 b7 b0 b7 c
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 114 freescale semiconductor rsp reset stack pointer (low byte) spl $ff (high byte not affected) inh 9c 1 p ? ? ? ? ? ? rti return from interrupt sp (sp) + $0001; pull (ccr) sp (sp) + $0001; pull (a) sp (sp) + $0001; pull (x) sp (sp) + $0001; pull (pch) sp (sp) + $0001; pull (pcl) inh 80 9 uuuuufppp rts return from subroutine sp sp + $0001 ; pull ( pch) sp sp + $0001; pull (pcl) inh 81 5 ufppp ? ? ? ? ? ? sbc # opr8i sbc opr8a sbc opr16a sbc oprx16 ,x sbc oprx8 ,x sbc ,x sbc oprx16 ,sp sbc oprx8 ,sp subtract with carry a (a) ? (m) ? (c) imm dir ext ix2 ix1 ix sp2 sp1 a2 b2 c2 d2 e2 f2 9e d2 9e e2 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ?? sec set c arry bit (c 1) inh 99 1 p ? ? ? ? ? 1 sei set interrupt mask bit (i 1) inh 9b 1 p ? ? 1 ? ? ? sta opr8a sta opr16a sta oprx16,x sta oprx8 ,x sta ,x sta oprx16,sp sta oprx8 ,sp store accumulator in memory m (a) dir ext ix2 ix1 ix sp2 sp1 b7 c7 d7 e7 f7 9e d7 9e e7 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 wpp pwpp pwpp wpp wp ppwpp pwpp 0 ? ? ? sthx opr8a sthx opr16a sthx oprx8 ,sp store h:x (index reg.) (m:m + $0001) (h:x) dir ext sp1 35 96 9e ff dd hh ll ff 4 5 5 wwpp pwwpp pwwpp 0 ? ? ? stop enable interrupts: stop processing refer to mcu documentation i bit 0; stop processing inh 8e 2 fp... ? ? 0 ? ? ? stx opr8a stx opr16a stx oprx16,x stx oprx8 ,x stx ,x stx oprx16,sp stx oprx8 ,sp store x (low 8 bits of index register) in memory m (x) dir ext ix2 ix1 ix sp2 sp1 bf cf df ef ff 9e df 9e ef dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 wpp pwpp pwpp wpp wp ppwpp pwpp 0 ? ? ? table 7-2. . instruction set summary (sheet 7 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr vh i n z c
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 115 sub # opr8i sub opr8a sub opr16a sub oprx16 ,x sub oprx8 ,x sub ,x sub oprx16 ,sp sub oprx8 ,sp subtract a (a) ? (m) imm dir ext ix2 ix1 ix sp2 sp1 a0 b0 c0 d0 e0 f0 9e d0 9e e0 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ?? swi software interrupt pc (pc) + $0001 push (pcl); sp (sp) ? $0001 push (pch); sp (sp) ? $0001 push (x); sp (sp) ? $0001 push (a); sp (sp) ? $0001 push (ccr); sp (sp) ? $0001 i 1; pch interrupt vector high byte pcl interrupt vector low byte inh 83 11 sssssvvfppp ? ? 1 ? ? ? tap transfer accumulator to ccr ccr (a) inh 84 1 p tax transfer accumulator to x (index register lo w) x (a) inh 97 1 p ? ? ? ? ? ? tpa transfer ccr to accumulator a (ccr) inh 85 1 p ? ? ? ? ? ? tst opr8a tsta tstx tst oprx8 ,x tst ,x tst oprx8 ,sp test for negative or zero (m) ? $00 (a) ? $00 (x) ? $00 (m) ? $00 (m) ? $00 (m) ? $00 dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e 6d dd ff ff 4 1 1 4 3 5 rfpp p p rfpp rfp prfpp 0 ? ? ? tsx transfer sp to index reg. h:x (sp) + $0001 inh 95 2 fp ? ? ? ? ? ? txa transfer x (index reg. low) to accumulator a (x) inh 9f 1 p ? ? ? ? ? ? table 7-2. . instruction set summary (sheet 8 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr vh i n z c
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 116 freescale semiconductor txs transfer index reg. to sp sp (h:x) ? $0001 inh 94 2 fp ? ? ? ? ? ? wait enable interrupts; wait for interrupt i bit 0; halt cpu inh 8f 2+ fp... ? ? 0 ? ? ? source form: everything in the source forms columns, except expressions in italic characters , is literal information which must appear in the assembly source file exactly as shown. the initial 3- to 5-letter mnemonic and the characters (# , ( ) and +) are always a literal characters. n any label or expression that evaluates to a single integer in the range 0-7. opr8i any label or expression that evaluates to an 8-bit immediate value. opr16i any label or expression that evaluates to a 16-bit immediate value. opr8a any label or expression that evaluates to an 8-bit direct-page address ($00xx). opr16a any label or expression that evaluates to a 16-bit address. oprx8 any label or expression that evaluates to an unsigned 8-bit value, us ed for indexed addressing. oprx16 any label or expression that evaluates to a 16-bit value, used for indexed addressing. rel any label or expression that refers to an address that is within ?128 to +127 locations from the start of the next instruction. operation symbols: a accumulator ccr condition code register h index register high byte m memory location n any bit opr operand (one or two bytes) pc program counter pch program counter high byte pcl program counter low byte rel relative program counter offset byte sp stack pointer spl stack pointer low byte x index register low byte & logical and | logical or logical exclusive or ( ) contents of + add ? subtract, negation (two?s complement) multiply divide # immediate value loaded with : concatenated with addressing modes: dir direct addressing mode ext extended addressing mode imm immediate addressing mode inh inherent addressing mode ix indexed, no offset addressing mode ix1 indexed, 8-bit offset addressing mode ix2 indexed, 16-bit offset addressing mode ix+ indexed, no offset, post increment addressing mode ix1+ indexed, 8-bit offset, post increment addressing mode rel relative addressing mode sp1 stack pointer, 8-bit offset addressing mode sp2 stack pointer 16-bit offset addressing mode cycle-by-cycle codes: f free cycle. this indicates a cycle where the cpu does not require use of the system buses. an f cycle is always one cycle of the system bus clock and is always a read cycle. p progryam fetch; read from next consecutive location in program memory r read 8-bit operand s push (write) one byte onto stack u pop (read) one byte from stack v read vector from $ffxx (high byte first) w write 8-bit operand ccr bits: voverflow bit h half-carry bit i interrupt mask n negative bit z zero bit c carry/borrow bit ccr effects: set or cleared ? not affected u undefined table 7-2. . instruction set summary (sheet 9 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr vh i n z c
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 117 table 7-3. opcode map (sheet 1 of 2) bit-manipulation branch read-modi fy-write control register/memory 00 5 brset0 3dir 10 5 bset0 2dir 20 3 bra 2rel 30 5 neg 2dir 40 1 nega 1inh 50 1 negx 1inh 60 5 neg 2ix1 70 4 neg 1ix 80 9 rti 1inh 90 3 bge 2rel a0 2 sub 2imm b0 3 sub 2dir c0 4 sub 3 ext d0 4 sub 3ix2 e0 3 sub 2ix1 f0 3 sub 1ix 01 5 brclr0 3dir 11 5 bclr0 2dir 21 3 brn 2rel 31 5 cbeq 3dir 41 4 cbeqa 3imm 51 4 cbeqx 3imm 61 5 cbeq 3ix1+ 71 5 cbeq 2ix+ 81 6 rts 1inh 91 3 blt 2rel a1 2 cmp 2imm b1 3 cmp 2dir c1 4 cmp 3 ext d1 4 cmp 3ix2 e1 3 cmp 2ix1 f1 3 cmp 1ix 02 5 brset1 3dir 12 5 bset1 2dir 22 3 bhi 2rel 32 5 ldhx 3ext 42 5 mul 1inh 52 6 div 1inh 62 1 nsa 1inh 72 1 daa 1inh 82 5+ bgnd 1inh 92 3 bgt 2rel a2 2 sbc 2imm b2 3 sbc 2dir c2 4 sbc 3 ext d2 4 sbc 3ix2 e2 3 sbc 2ix1 f2 3 sbc 1ix 03 5 brclr1 3dir 13 5 bclr1 2dir 23 3 bls 2rel 33 5 com 2dir 43 1 coma 1inh 53 1 comx 1inh 63 5 com 2ix1 73 4 com 1ix 83 11 swi 1inh 93 3 ble 2rel a3 2 cpx 2imm b3 3 cpx 2dir c3 4 cpx 3 ext d3 4 cpx 3ix2 e3 3 cpx 2ix1 f3 3 cpx 1ix 04 5 brset2 3dir 14 5 bset2 2dir 24 3 bcc 2rel 34 5 lsr 2dir 44 1 lsra 1inh 54 1 lsrx 1inh 64 5 lsr 2ix1 74 4 lsr 1ix 84 1 ta p 1inh 94 2 txs 1inh a4 2 and 2imm b4 3 and 2dir c4 4 and 3 ext d4 4 and 3ix2 e4 3 and 2ix1 f4 3 and 1ix 05 5 brclr2 3dir 15 5 bclr2 2dir 25 3 bcs 2rel 35 4 sthx 2dir 45 3 ldhx 3imm 55 4 ldhx 2dir 65 3 cphx 3imm 75 5 cphx 2dir 85 1 tpa 1inh 95 2 tsx 1inh a5 2 bit 2imm b5 3 bit 2dir c5 4 bit 3 ext d5 4 bit 3ix2 e5 3 bit 2ix1 f5 3 bit 1ix 06 5 brset3 3dir 16 5 bset3 2dir 26 3 bne 2rel 36 5 ror 2dir 46 1 rora 1inh 56 1 rorx 1inh 66 5 ror 2ix1 76 4 ror 1ix 86 3 pula 1inh 96 5 sthx 3ext a6 2 lda 2imm b6 3 lda 2dir c6 4 lda 3 ext d6 4 lda 3ix2 e6 3 lda 2ix1 f6 3 lda 1ix 07 5 brclr3 3dir 17 5 bclr3 2dir 27 3 beq 2rel 37 5 asr 2dir 47 1 asra 1inh 57 1 asrx 1inh 67 5 asr 2ix1 77 4 asr 1ix 87 2 psha 1inh 97 1 ta x 1inh a7 2 ais 2imm b7 3 sta 2dir c7 4 sta 3 ext d7 4 sta 3ix2 e7 3 sta 2ix1 f7 2 sta 1ix 08 5 brset4 3dir 18 5 bset4 2dir 28 3 bhcc 2rel 38 5 lsl 2dir 48 1 lsla 1inh 58 1 lslx 1inh 68 5 lsl 2ix1 78 4 lsl 1ix 88 3 pulx 1inh 98 1 clc 1inh a8 2 eor 2imm b8 3 eor 2dir c8 4 eor 3 ext d8 4 eor 3ix2 e8 3 eor 2ix1 f8 3 eor 1ix 09 5 brclr4 3dir 19 5 bclr4 2dir 29 3 bhcs 2rel 39 5 rol 2dir 49 1 rola 1inh 59 1 rolx 1inh 69 5 rol 2ix1 79 4 rol 1ix 89 2 pshx 1inh 99 1 sec 1inh a9 2 adc 2imm b9 3 adc 2dir c9 4 adc 3 ext d9 4 adc 3ix2 e9 3 adc 2ix1 f9 3 adc 1ix 0a 5 brset5 3dir 1a 5 bset5 2dir 2a 3 bpl 2rel 3a 5 dec 2dir 4a 1 deca 1inh 5a 1 decx 1inh 6a 5 dec 2ix1 7a 4 dec 1ix 8a 3 pulh 1inh 9a 1 cli 1inh aa 2 ora 2imm ba 3 ora 2dir ca 4 ora 3 ext da 4 ora 3ix2 ea 3 ora 2ix1 fa 3 ora 1ix 0b 5 brclr5 3dir 1b 5 bclr5 2dir 2b 3 bmi 2rel 3b 7 dbnz 3dir 4b 4 dbnza 2inh 5b 4 dbnzx 2inh 6b 7 dbnz 3ix1 7b 6 dbnz 2ix 8b 2 pshh 1inh 9b 1 sei 1inh ab 2 add 2imm bb 3 add 2dir cb 4 add 3 ext db 4 add 3ix2 eb 3 add 2ix1 fb 3 add 1ix 0c 5 brset6 3dir 1c 5 bset6 2dir 2c 3 bmc 2rel 3c 5 inc 2dir 4c 1 inca 1inh 5c 1 incx 1inh 6c 5 inc 2ix1 7c 4 inc 1ix 8c 1 clrh 1inh 9c 1 rsp 1inh bc 3 jmp 2dir cc 4 jmp 3 ext dc 4 jmp 3ix2 ec 3 jmp 2ix1 fc 3 jmp 1ix 0d 5 brclr6 3dir 1d 5 bclr6 2dir 2d 3 bms 2rel 3d 4 tst 2dir 4d 1 tsta 1inh 5d 1 tstx 1inh 6d 4 tst 2ix1 7d 3 tst 1ix 9d 1 nop 1inh ad 5 bsr 2rel bd 5 jsr 2dir cd 6 jsr 3 ext dd 6 jsr 3ix2 ed 5 jsr 2ix1 fd 5 jsr 1ix 0e 5 brset7 3dir 1e 5 bset7 2dir 2e 3 bil 2rel 3e 6 cphx 3ext 4e 5 mov 3dd 5e 5 mov 2dix+ 6e 4 mov 3imd 7e 5 mov 2ix+d 8e 2+ stop 1inh 9e page 2 ae 2 ldx 2imm be 3 ldx 2dir ce 4 ldx 3 ext de 4 ldx 3ix2 ee 3 ldx 2ix1 fe 3 ldx 1ix 0f 5 brclr7 3dir 1f 5 bclr7 2dir 2f 3 bih 2rel 3f 5 clr 2dir 4f 1 clra 1inh 5f 1 clrx 1inh 6f 5 clr 2ix1 7f 4 clr 1ix 8f 2+ wait 1inh 9f 1 txa 1inh af 2 aix 2imm bf 3 stx 2dir cf 4 stx 3 ext df 4 stx 3ix2 ef 3 stx 2ix1 ff 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment opcode in hexadecimal number of bytes f0 3 sub 1ix hcs08 cycles instruction mnemonic addressing mode
chapter 7 central processor unit (s08cpuv2) MC9S08JM16 series data sheet, rev. 2 118 freescale semiconductor bit-manipulation branch read-modi fy-write control register/memory 9e60 6 neg 3sp1 9ed0 5 sub 4sp2 9ee0 4 sub 3sp1 9e61 6 cbeq 4sp1 9ed1 5 cmp 4sp2 9ee1 4 cmp 3sp1 9ed2 5 sbc 4sp2 9ee2 4 sbc 3sp1 9e63 6 com 3sp1 9ed3 5 cpx 4sp2 9ee3 4 cpx 3sp1 9ef3 6 cphx 3sp1 9e64 6 lsr 3sp1 9ed4 5 and 4sp2 9ee4 4 and 3sp1 9ed5 5 bit 4sp2 9ee5 4 bit 3sp1 9e66 6 ror 3sp1 9ed6 5 lda 4sp2 9ee6 4 lda 3sp1 9e67 6 asr 3sp1 9ed7 5 sta 4sp2 9ee7 4 sta 3sp1 9e68 6 lsl 3sp1 9ed8 5 eor 4sp2 9ee8 4 eor 3sp1 9e69 6 rol 3sp1 9ed9 5 adc 4sp2 9ee9 4 adc 3sp1 9e6a 6 dec 3sp1 9eda 5 ora 4sp2 9eea 4 ora 3sp1 9e6b 8 dbnz 4sp1 9edb 5 add 4sp2 9eeb 4 add 3sp1 9e6c 6 inc 3sp1 9e6d 5 tst 3sp1 9eae 5 ldhx 2ix 9ebe 6 ldhx 4ix2 9ece 5 ldhx 3ix1 9ede 5 ldx 4sp2 9eee 4 ldx 3sp1 9efe 5 ldhx 3sp1 9e6f 6 clr 3sp1 9edf 5 stx 4sp2 9eef 4 stx 3sp1 9eff 5 sthx 3sp1 inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment note: all sheet 2 opcodes are preceded by the page 2 prebyte (9e) prebyte (9e) and opcode in hexadecimal number of bytes 9e60 6 neg 3sp1 hcs08 cycles instruction mnemonic addressing mode table 7-3. opcode map (sheet 2 of 2)
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 119 chapter 8 keyboard interrupt (s08kbiv2) 8.1 introduction the MC9S08JM16 series have one kbi module with seven keyboard interrupt inputs. see chapter 2, ?pins and connections ,? for more information about the logi c and hardware aspects of these pins. note MC9S08JM16 series devices operate at a higher voltage range (2.7 v to 5.5 v) and do not include stop1 mode . therefore, please disregard references to stop1.
keyboard interrupt (kbi) modulechapter 8 keyboard interrupt (s08kbiv2) MC9S08JM16 series data sheet, rev. 2 120 freescale semiconductor figure 8-1. MC9S08JM16 series block diagram highlighting kbi block and pins ptc1/sda ptc0/scl v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta5, pta0 pte0/txd1 pte1/rxd1 ptd1/adp9/acmp? ptd0/adp8/acmp+ ptc5/rxd2 ptc4 ptc3/txd2 ptc2 port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi1) user flash (in bytes) user ram (in bytes) on-chip ice and debug module (dbg) hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pu llup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. pin contains integrated pullup device. 5. when pin functions as kbi (kbipen = 1) and associated pin is configured to enable the pullup device, kbedgn can be used to reco nfigure the pullup as a pulldown device. 2-channel timer/pwm module (tpm2) ptb5/kbip5/adp5 port b pte5/mosi1 pte4/miso1 pte6/spsck1 pte7/ss1 hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset v ssad v ddad v refh analog-to-digital converter (adc) 4-channel timer/pwm module (tpm1) ptd7 2 ptb4/kbip4/adp4 ptg3/kbip7 ptg2/kbip6 port g 8-channel, 12-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg4/xtal ptg5/extal irq/tpmclk rxd2 txd2 sda scl 6 kbipx kbipx tpmclk spsck1 ss1 miso1 mosi1 tpmclk tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 2 4 usb sie usb endpoint ram full speed usb transceiver usbdp usbdn miso2 ss2 spsck2 mosi2 ptb1/mosi2/adp1 ptb0/miso2/adp0 8-/16-bit real-time counter (rtc) ptb3/ss2 /adp3 ptb2/spsck2/adp2 tpm1chx 3 tpm2ch1 tpm2ch0 2 analog comparator (acmp) system usb 3.3 v voltage regulator v usb33 1024 acmpo acmp+ acmp? ptd2/kbip2/acmpo 8-/16-bit serial peripheral interface module (spi2) mc9s08jm8 = 8,192 MC9S08JM16 = 16,384 v ssosc
keyboard interrupts (s08kbiv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 121 8.1.1 features the kbi features include: ? up to eight keyboard interrupt pins with individual pin enable bits. ? each keyboard interrupt pin is pr ogrammable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity. ? one software enabled keyboard interrupt. ? exit from low-power modes. 8.1.2 modes of operation this section defines the kbi operation in wait, stop, and background debug modes. 8.1.2.1 kbi in wait mode the kbi continues to operate in wa it mode if enabled before executi ng the wait instru ction. therefore, an enabled kbi pin (kbpex = 1) can be used to bri ng the mcu out of wait mode if the kbi interrupt is enabled (kbie = 1). 8.1.2.2 kbi in stop modes the kbi operates asynchronously in stop3 mode if enabled before executing the stop instruction. therefore, an enabled kbi pin (kbp ex = 1) can be used to bring th e mcu out of stop3 mode if the kbi interrupt is enabled (kbie = 1). during either stop1 or stop2 mode, the kbi is disabled. in some systems, the pins associated with the kbi may be sources of wakeup from stop1 or stop2, see the stop modes section in the modes of operation chapter. upon wake-up from stop1 or stop2 mode, the kbi modul e will be in the reset state. 8.1.2.3 kbi in active background mode when the microcontroller is in ac tive background mode, the kbi will continue to operate normally. 8.1.3 block diagram the block diagram for the keyboa rd interrupt module is shown figure 8-2 .
keyboard interrupts (s08kbiv2) MC9S08JM16 series data sheet, rev. 2 122 freescale semiconductor figure 8-2. kbi block diagram 8.2 external signal description the kbi input pins can be us ed to detect either falling edges, or both falli ng edge and low level interrupt requests. the kbi input pins can also be used to detect either rising edges, or both rising edge and high level interrupt requests. the signal properties of kbi are shown in table 8-1 . 8.3 register definition the kbi includes three registers: ? an 8-bit pin status and control register. ? an 8-bit pin enable register. ? an 8-bit edge select register. refer to the direct-page register summary in the memory chapter for the absolute address assignments for all kbi registers. this section refers to re gisters and control bits only by their names. some mcus may have more than one kbi, so register names include placeholder characters to identify which kbi is being referenced. 8.3.1 kbi status and control register (kbisc) kbisc contains the status flag and control bits, which are used to configure the kbi. table 8-1. signal properties signal function i/o kbipn keyboard interrupt pins i dq ck clr v dd kbmod kbie keyboard interrupt ff kback reset synchronizer kbf stop bypass stop busclk kbipen 0 1 s kbedgn kbipe0 0 1 s kbedg0 kbi p0 kbi pn kbi interrupt reques t
keyboard interrupts (s08kbiv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 123 8.3.2 kbi pin enable register (kbipe) kbipe contains the pin enable control bits. 8.3.3 kbi edge select register (kbies) kbies contains the edge select control bits. 76543210 r 0 0 0 0 kbf 0 kbie kbmod w kback r e s e t :00000000 = unimplemented figure 8-3. kbi status and control register table 8-2. kbisc register field descriptions field description 7:4 unused register bits, always read 0. 3 kbf keyboard interrupt flag ? kbf indicates when a keyb oard interrupt is detected. wr ites have no effect on kbf. 0 no keyboard interrupt detected. 1 keyboard interrupt detected. 2 kback keyboard acknowledge ? writing a 1 to kback is part of the flag clearing mechanism. kback always reads as 0. 1 kbie keyboard interrupt enable ? kbie determines whether a keyboard interrupt is requested. 0 keyboard interrupt request not enabled. 1 keyboard interrupt request enabled. 0 kbmod keyboard detection mode ? kbmod (along with the kbedg bits) contro ls the detection mode of the keyboard interrupt pins.0keyboard detects edges only. 1 keyboard detects both edges and levels. 76543210 r kbipe7 kbipe6 kbipe5 kbipe4 kbipe3 kbipe2 kbipe1 kbipe0 w r e s e t :00000000 figure 8-4. kbi pin enable register table 8-3. kbipe register field descriptions field description 7:0 kbipen keyboard pin enables ? each of the kbipen bits enable the corresponding keyboard interrupt pin. 0 pin not enabled as keyboard interrupt. 1 pin enabled as keyboard interrupt.
keyboard interrupts (s08kbiv2) MC9S08JM16 series data sheet, rev. 2 124 freescale semiconductor 8.4 functional description this on-chip peripheral module is called a keyboard interrupt (kbi) module because originally it was designed to simplify the c onnection and use of row-column matrices of keyboard switches. however, these inputs are also useful as extra external interrupt i nputs and as an external m eans of waking the mcu from stop or wait low-power modes. the kbi module allows up to eight pins to act as additional interrupt s ources. writing to the kbipen bits in the keyboard interrupt pin enable register (kbipe ) independently enables or disables each kbi pin. each kbi pin can be confi gured as edge sensitive or edge and level sensitive based on the kbmod bit in the keyboard interrupt status and control register (kbi sc). edge sensitive can be software programmed to be either falling or rising; the leve l can be either low or high. the polar ity of the edge or edge and level sensitivity is selected using the kbedgn bits in the keyboard interrupt edge select register (kbies). 8.4.1 edge only sensitivity synchronous logic is used to detect edges. a falling edge is detected when an enabled keyboard interrupt (kbipen=1) input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. a rising edge is detected when the input signal is seen as a logic 0 (the deasserted level) during one bus cycle and then a logic 1 (the asserted level) during the next cycle.before the first edge is detected, all enabled keyboard interrupt input signals must be at the deasserted logic levels. afte r any edge is detected, all enabled keyboa rd interrupt input signals must return to the deasserted level before any new edge can be detected. a valid edge on an enabled kb i pin will set kbf in kbis c. if kbie in kbisc is set, an interrupt request will be presented to the cpu. cl earing of kbf is accomplished by writing a 1 to kback in kbisc. 8.4.2 edge and level sensitivity a valid edge or level on an enabled kbi pin will set kb f in kbisc. if kbie in kbisc is set, an interrupt request will be presented to th e cpu. clearing of kbf is accompli shed by writing a 1 to kback in 76543210 r kbedg7 kbedg6 kbedg5 kbedg4 kbedg3 kbedg2 kbedg1 kbedg0 w r e s e t :00000000 figure 8-5. kbi edge select register table 8-4. kbies register field descriptions field description 7:0 kbedgn keyboard edge selects ? each of the kbedgn bits selects the falling edge/low level or rising edge/high level function of the corresponding pin). 0 falling edge/low level. 1 rising edge/high level.
keyboard interrupts (s08kbiv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 125 kbisc provided all enabled keyboard inputs are at their deasserted le vels. kbf will remain set if any enabled kbi pin is asserted while atte mpting to clear by writing a 1 to kback. 8.4.3 kbi pullup/pulldown resistors the kbi pins can be configured to use an internal pullup/pulldown resistor using the associated i/o port pullup enable register. if an internal resistor is enab led, the kbies register is used to select whether the resistor is a pullup (kbedgn = 0) or a pulldown (kbedgn = 1). 8.4.4 kbi initialization when a keyboard interrupt pin is first enabled it is possible to get a false keyboard interrupt flag. to prevent a false interrupt request during keyboard initialization, the user must do the following: 1. mask keyboard interrupts by clearing kbie in kbisc. 2. enable the kbi polarity by setting th e appropriate kbedgn bits in kbies. 3. if using internal pullup/pulldow n device, configure the associated pullup enable bits in ptxpe. 4. enable the kbi pins by setting th e appropriate kbipen bits in kbipe. 5. write to kback in kbisc to clear any false interrupts. 6. set kbie in kbisc to enable interrupts.
keyboard interrupts (s08kbiv2) MC9S08JM16 series data sheet, rev. 2 126 freescale semiconductor
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 127 chapter 9 5 v analog comparator (s08acmpv2) 9.1 introduction the analog comparator module (acmp) provides a circuit fo r comparing two analog input voltages or for comparing one analog input voltage to an internal refe rence voltage. the comparator circuit is designed to operate across the full range of the supply voltage (rail to rail operation). note MC9S08JM16 series devices operate at a higher voltage range (2.7 v to 5.5 v) and do not include stop1 mode . therefore, please disregard references to stop1. 9.1.1 acmp configuration information when using the bandgap reference voltage for input to acmp+, the user must enable the bandgap buffer by setting bgbe =1 in spmsc1 see section 5.7.7, ?system power manage ment status and control 1 register (spmsc1) ?. for value of bandgap voltage reference see appendix a.6, ?dc characteristics .? 9.1.2 acmp/tpm configuration information the acmp module can be configured to connect the output of the anal og comparator to tpm input capture channel 0 by setting acic in sopt2. with acic se t, the tpm1ch0 pin is not available externally regardless of the configuration of the tpm module.
chapter 9 5 v analog comparator (s08acmpv2) MC9S08JM16 series data sheet, rev. 2 128 freescale semiconductor figure 9-1. MC9S08JM16 series block diagram highlighting acmp block and pins ptc1/sda ptc0/scl v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta5, pta0 pte0/txd1 pte1/rxd1 ptd1/adp9/acmp? ptd0/adp8/acmp+ ptc5/rxd2 ptc4 ptc3/txd2 ptc2 port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi1) user flash (in bytes) user ram (in bytes) on-chip ice and debug module (dbg) hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pu llup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. pin contains integrated pullup device. 5. when pin functions as kbi (kbipen = 1) and associated pin is configured to enable the pullup device, kbedgn can be used to reco nfigure the pullup as a pulldown device. 2-channel timer/pwm module (tpm2) ptb5/kbip5/adp5 port b pte5/mosi1 pte4/miso1 pte6/spsck1 pte7/ss1 hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset v ssad v ddad v refh analog-to-digital converter (adc) 4-channel timer/pwm module (tpm1) ptd7 2 ptb4/kbip4/adp4 ptg3/kbip7 ptg2/kbip6 port g 8-channel, 12-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg4/xtal ptg5/extal irq/tpmclk rxd2 txd2 sda scl 6 kbipx kbipx tpmclk spsck1 ss1 miso1 mosi1 tpmclk tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 2 4 usb sie usb endpoint ram full speed usb transceiver usbdp usbdn miso2 ss2 spsck2 mosi2 ptb1/mosi2/adp1 ptb0/miso2/adp0 8-/16-bit real-time counter (rtc) ptb3/ss2 /adp3 ptb2/spsck2/adp2 tpm1chx 3 tpm2ch1 tpm2ch0 2 analog comparator (acmp) system usb 3.3 v voltage regulator v usb33 1024 acmpo acmp+ acmp? ptd2/kbip2/acmpo 8-/16-bit serial peripheral interface module (spi2) mc9s08jm8 = 8,192 MC9S08JM16 = 16,384 v ssosc
analog comparator (s08acmpv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 129 9.1.3 features the acmp has the following features: ? full rail to ra il supply operation. ? selectable interrupt on rising edge , falling edge, or either rising or falling edges of comparator output. ? option to compare to fixed internal bandgap reference voltage. ? option to allow comparator outpu t to be visible on a pin, acmpo. ? can operate in stop3 mode 9.1.4 modes of operation this section defines the acmp operatio n in wait, stop and background debug modes. 9.1.4.1 acmp in wait mode the acmp continues to run in wait mode if enable d before executing the wait instruction. therefore, the acmp can be used to bring the mcu out of wait mode if the acmp interrupt, acie is enabled. for lowest possible current c onsumption, the acmp must be disabled by software if not required as an interrupt source during wait mode. 9.1.4.2 acmp in stop modes 9.1.4.2.1 stop3 mode operation the acmp continues to operate in stop3 mode if enabled and compare operation remains active. if acope is enabled, comparator output operates as in the normal operating mode and comparator output is placed onto the external pin. the mcu is brought out of stop when a compare event occurs and acie is enabled; acf flag sets accordingly. if stop is exited with a reset, the ac mp will be put into its reset state. 9.1.4.2.2 stop2 and st op1 mode operation during either stop2 and stop1 mode, the acmp module will be fully powered down. upon wake-up from stop2 or stop1 mode, the acmp modul e will be in the reset state. 9.1.4.3 acmp in active background mode when the microcontroller is in ac tive background mode, the acmp wi ll continue to operate normally. 9.1.5 block diagram the block diagram for the anal og comparator module is shown figure 9-2 .
analog comparator (s08acmpv2) MC9S08JM16 series data sheet, rev. 2 130 freescale semiconductor figure 9-2. analog comparator 5v (acmp5) block diagram 9.2 external signal description the acmp has two analog input pi ns, acmp+ and acmp? and one digi tal output pin acmpo. each of these pins can accept an input voltage that varies ac ross the full operating voltage range of the mcu. as shown in figure 9-2 , the acmp? pin is connected to the inve rting input of the comparator, and the acmp+ pin is connected to the comparator non-i nverting input if acbgs is a 0. as shown in figure 9-2 , the acmpo pin can be enabled to drive an external pin. the signal properties of acmp are shown in table 9-1 . 9.3 memory map 9.3.1 register descriptions the acmp includes one register: table 9-1. signal properties signal function i/o acmp? inverting analog input to the acmp. (minus input) i acmp+ non-inverting analog input to the acmp. (positive input) i acmpo digital output of the acmp. o + - interrupt control internal reference acbgs internal bus status & control register acmod set acf acme acf acie acope comparator acmp interrupt request acmp+ acmp? acmpo
analog comparator (s08acmpv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 131 ? an 8-bit status and control register refer to the direct-page register summ ary in the memory section of this data sheet for the absolute address assignments for all acmp registers. this section refers to registers and control bits only by their names. some mcus may have more than one acmp, so regist er names include placeholde r characters to identify which acmp is being referenced. 9.3.1.1 acmp status and control register (acmpsc) acmpsc contains the status flag and control bits which are used to enable and configure the acmp. 76543210 r acme acbgs acf acie aco acope acmod w r e s e t :00000000 = unimplemented figure 9-3. acmp status and control register table 9-2. acmp status and control register field descriptions field description 7 acme analog comparator module enable ? acme enables the acmp module. 0 acmp not enabled 1 acmp is enabled 6 acbgs analog comparator bandgap select ? acbgs is used to select between the bandgap reference voltage or the acmp+ pin as the input to the non- inverting input of the analog comparatorr. 0 external pin acmp+ selected as non-inverting input to comparator 1 internal reference select as non-inverting input to comparator note: refer to this chapter introduction to verify if any other config bits are necessary to enable the bandgap reference in the chip level. 5 acf analog comparator flag ? acf is set when a compare event occu rs. compare events are defined by acmod. acf is cleared by writing a one to acf. 0 compare event has not occurred 1 compare event has occurred 4 acie analog comparator interrupt enable ? acie enables the interrupt from the acmp. when acie is set, an interrupt will be asserted when acf is set. 0 interrupt disabled 1 interrupt enabled 3 aco analog comparator output ? reading aco will return the current value of the analog comparator output. aco is reset to a 0 and will read as a 0 when the acmp is disabled (acme = 0).
analog comparator (s08acmpv2) MC9S08JM16 series data sheet, rev. 2 132 freescale semiconductor 9.4 functional description the analog comparator can be used to compare two analog input volta ges applied to acmp+ and acmp?; or it can be used to compare an analog input voltage applie d to acmp? with an in ternal bandgap reference voltage. acbgs is used to select between the bandga p reference voltage or th e acmp+ pin as the input to the non-inverting input of the analog comparator. the comparator output is high when the non-inverting input is greater than the inverting input, and is low when the non-invertin g input is less than the inverting input. acmod is used to select the condition which will cause acf to be set. acf can be set on a rising edge of the comparator out put, a falling edge of the comparator output, or either a rising or a falling edge (toggle). the comparator output can be read directly through aco. the comparator output can be driven onto the acmpo pin using acope. 2 acope analog comparator output pin enable ? acope is used to enable the comparator output to be placed onto the external pin, acmpo. 0 analog comparator output not available on acmpo 1 analog comparator output is driven out on acmpo 1:0 acmod analog comparator mode ? acmod selects the type of co mpare event which sets acf. 00 encoding 0 ? comparator output falling edge 01 encoding 1 ? comparator output rising edge 10 encoding 2 ? comparator output falling edge 11 encoding 3 ? comparator output rising or falling edge table 9-2. acmp status and control register field descriptions (continued) field description
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 133 chapter 10 analog-to-digital converter (s08adc12v1) 10.1 overview the 12-bit analog-to-digital convert er (adc) is a successive appr oximation adc desi gned for operation within an integrated micr ocontroller system-on-chip. note MC9S08JM16 series devices operate at a higher voltage range (2.7 v to 5.5 v) and do not include stop1 mode . therefore, please disregard references to stop1. 10.1.1 module configurations this section provides information for configuring the adc on this device. 10.1.1.1 channel assignments the adc channel assignments for the MC9S08JM16 se ries devices are shown in the table below. reserved channels convert to an unknown value. table 10-1. adc channel assignment adch channel input pi n control adch channel input pin control 00000 ad0 ptb0/miso2/adp0 adpc0 10000 ad16 v refl n/a 00001 ad1 ptb1/mosi2/adp1 adpc1 10001 ad17 v refl n/a 00010 ad2 ptb2/spsck2/a dp2 adpc2 10010 ad18 v refl n/a 00011 ad3 ptb3/ss2 /adp3 adpc3 10011 ad19 v refl n/a 00100 ad4 ptb4/kbip4/adp4 adpc4 10100 ad20 v refl n/a 00101 ad5 ptb5/kbip5/adp5 adpc5 10101 ad21 v refl n/a 00110 ad6 v refl adpc6 10110 ad22 reserved n/a 00111 ad7 v refl adpc7 10111 ad23 reserved n/a 01000 ad8 ptd0/adp8/acmp+ adpc8 11000 ad24 reserved n/a 01001 ad9 ptd1/adp9/acmp? adpc9 11001 ad25 reserved n/a 01010 ad10 v refl adpc10 11010 ad26 temperature sensor 1 n/a 01011 ad11 v refl adpc11 11011 ad27 internal bandgap n/a 01100 ad12 v refl adpc12 11100 reserved n/a 01101 ad13 v refl adpc13 11101 v refh v refh n/a 01110 ad14 v refl adpc14 11110 v refl v refl n/a
chapter 10 analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 134 freescale semiconductor note selecting the internal bandgap channe l requires bgbe =1 in spmsc1, see section 5.7.7, ?system power management status and control 1 register (spmsc1) .? for value of bandgap voltage reference see appendix a.8, ?analog comparator (acmp) electricals .? 10.1.1.2 alternate clock the adc module is capable of perf orming conversions using the mcu bus clock, the bus clock divided by two, the local asynchronous clock ( adack) within the module, or th e alternate clock (altclk). the altclk on this devi ce is mcgerclk. the selected clock source mu st run at a frequency such that the adc conversion clock (adck) runs at a frequency within its specified range (f adck ) after being divided down fr om the altclk input as determined by the adiv bits. altclk is active while the mcu is in wait mode provided the conditi ons described above are met. this allows altclk to be used as the conversion clock source for the adc while the mcu is in wait mode. altclk cannot be used as the adc conversi on clock source while the mcu is in stop3. 10.1.1.3 hardware trigger the rtc on this device can be enabled as a hard ware trigger for the adc module by setting the adcsc2[adtrg] bit. when enabled, the adc will be triggered every time rtcint matches rtcmod. the rtc interrupt does not have to be enabled to trigger the adc. the rtc can be configured to cause a ha rdware trigger in mcu run, wait, and stop3. 10.1.1.4 analog pin enables the adc on MC9S08JM16 series c ontain only two analog pin enable registers, apctl1 and apctl2. 10.1.1.5 temperature sensor the adc module includes a temperature sensor whos e output is connected to one of the adc analog channel inputs. equation 10-1 provides an approximate transfer function of the te mperature sensor. temp = 25 ? ((v temp ? v temp25 ) m) eqn. 10-1 where: ?v temp is the voltage of the temperature sens or channel at the ambient temperature. 01111 ad15 v refl adpc15 11111 module disabled none n/a 1 for more information, see section 10.1.1.5, ?temperature sensor .? table 10-1. adc channel assignment (continued) adch channel input pi n control adch channel input pin control
chapter 10 analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 135 ?v temp25 is the voltage of the temperature sensor channel at 25 c. ? m is the hot or cold voltage versus temperature slope in v/ c. for temperature calculations, use the v temp25 and m values from the appendix a.9, ?adc characteristics .? in application code, the us er reads the temperature se nsor channel, calculates v temp , and compares to v temp25 . if v temp is greater than v temp25, the cold slope value is applied in equation 10-1 . if v temp is less than v temp25, the hot slope value is applied in equation 10-1 . to improve accuracy, calibrate th e bandgap voltage reference and temperature se nsor. calibrating at 25 c will improve accuracy to 4.5 c. calibrating at 3 points, ?40 c, 25 c, and 125c will improve accuracy to 2.5 c. once calibration has been comp leted, the user needs to calculate the slope for both hot and cold. in application code, the user would then calculate the temperature using equation 10-1 as detailed above and then determine if the temperature is above or below 25 c. once determined, the user can recalculate the temperature using the hot or cold slope value obtained during calibration. 10.1.2 low-power mode operation the adc is capable of running in stop3 mode but requires lvdse a nd lvde in spmsc1 to be set.
chapter 10 analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 136 freescale semiconductor figure 10-1. MC9S08JM16 series block di agram highlighting adc block and pins ptc1/sda ptc0/scl v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta5, pta0 pte0/txd1 pte1/rxd1 ptd1/adp9/acmp? ptd0/adp8/acmp+ ptc5/rxd2 ptc4 ptc3/txd2 ptc2 port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi1) user flash (in bytes) user ram (in bytes) on-chip ice and debug module (dbg) hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pu llup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. pin contains integrated pullup device. 5. when pin functions as kbi (kbipen = 1) and associated pin is configured to enable the pullup device, kbedgn can be used to reco nfigure the pullup as a pulldown device. 2-channel timer/pwm module (tpm2) ptb5/kbip5/adp5 port b pte5/mosi1 pte4/miso1 pte6/spsck1 pte7/ss1 hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset v ssad v ddad v refh analog-to-digital converter (adc) 4-channel timer/pwm module (tpm1) ptd7 2 ptb4/kbip4/adp4 ptg3/kbip7 ptg2/kbip6 port g 8-channel, 12-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg4/xtal ptg5/extal irq/tpmclk rxd2 txd2 sda scl 6 kbipx kbipx tpmclk spsck1 ss1 miso1 mosi1 tpmclk tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 2 4 usb sie usb endpoint ram full speed usb transceiver usbdp usbdn miso2 ss2 spsck2 mosi2 ptb1/mosi2/adp1 ptb0/miso2/adp0 8-/16-bit real-time counter (rtc) ptb3/ss2 /adp3 ptb2/spsck2/adp2 tpm1chx 3 tpm2ch1 tpm2ch0 2 analog comparator (acmp) system usb 3.3 v voltage regulator v usb33 1024 acmpo acmp+ acmp? ptd2/kbip2/acmpo 8-/16-bit serial peripheral interface module (spi2) mc9s08jm8 = 8,192 MC9S08JM16 = 16,384 v ssosc
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 137 10.1.3 features features of the adc module include: ? linear successive approximation algorithm with 12-bit resolution ? up to 28 analog inputs ? output formatted in 12-, 10-, or 8- bit right-justified unsigned format ? single or continuous conversion (automatic return to idle af ter single conversion) ? configurable sample time and conversion speed/power ? conversion complete flag and interrupt ? input clock selectable from up to four sources ? operation in wait or stop3 m odes for lower noise operation ? asynchronous clock source for lower noise operation ? selectable asynchronous hardware conversion trigger ? automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value ? temperature sensor 10.1.4 adc module block diagram figure 10-2 provides a block diagram of the adc module .
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 138 freescale semiconductor figure 10-2. adc block diagram 10.2 external signal description the adc module supports up to 28 se parate analog inputs. it also re quires four supply/reference/ground connections. table 10-2. signal properties name function ad27 ? ad0 analog channel inputs v refh high reference voltage v refl low reference voltage v ddad analog power supply v ssad analog ground ad0 ? ? ? ad27 v refh v refl advin adch control sequencer initialize sample convert transfer abort clock divide adck 2 async clock gen bus clock altclk adiclk adiv adack adco adlsmp adlpc mode complete data registers sar converter compare value registers compare value sum aien coco interrupt aien coco adtrg 1 2 1 2 mcu stop adhwt logic acfgt 3 compare true 3 compare true adccfg adcsc1 adcsc2
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 139 10.2.1 analog power (v ddad ) the adc analog portion uses v ddad as its power connection. in some packages, v ddad is connected internally to v dd . if externally available, connect the v ddad pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddad for good results. 10.2.2 analog ground (v ssad ) the adc analog portion uses v ssad as its ground connection. in some packages, v ssad is connected internally to v ss . if externally available, connect the v ssad pin to the same voltage potential as v ss . 10.2.3 voltage reference high (v refh ) v refh is the high reference voltage for the converter . in some packages, v refh is connected internally to v ddad . if externally available, v refh may be connected to the same potential as v ddad or may be driven by an external source between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). 10.2.4 voltage reference low (v refl ) v refl is the low-reference voltage for th e converter. in some packages, v refl is connected internally to v ssad . if externally available, connect the v refl pin to the same voltage potential as v ssad . 10.2.5 analog channel inputs (adx) the adc module supports up to 28 separate analog input s. an input is selected for conversion through the adch channel select bits. 10.3 register definition these memory-mapped registers contro l and monitor operation of the adc: ? status and control register, adcsc1 ? status and control register, adcsc2 ? data result registers, adcrh and adcrl ? compare value registers, adccvh and adccvl ? configuration register, adccfg ? pin control registers, apctl1, apctl2, apctl3 10.3.1 status and contro l register 1 (adcsc1) this section describes the functi on of the adc status and control register (adcsc1). writing adcsc1 aborts the current c onversion and initiates a new c onversion (if the adch bits are equal to a value other than all 1s).
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 140 freescale semiconductor 7654 3 210 rcoco aien adco adch w r e s e t :0001 1 111 figure 10-3. status and control register (adcsc1) table 10-3. adcsc1 field descriptions field description 7 coco conversion complete flag. the coco flag is a read-only bit set each time a conversion is completed when the compare function is disabled (acfe = 0). when the compar e function is enabled (acfe = 1), the coco flag is set upon completion of a conversion only if the compare result is true. this bit is cleared when adcsc1 is written or when adcrl is read. 0 conversion not completed 1 conversion completed 6 aien interrupt enable aien enables conversion complete in terrupts. when coco becomes set while aien is high, an interrupt is asserted. 0 conversion complete interrupt disabled 1 conversion complete interrupt enabled 5 adco continuous conversion enable. adco enables continuous conversions. 0 one conversion following a write to the adcsc1 when software triggered operation is selected, or one conversion following assertion of adhwt when hardware triggered operation is selected. 1 continuous conversions initiated following a write to adcsc1 when software triggered operation is selected. continuous conversions are initiated by an adhwt event when hardware triggered operation is selected. 4:0 adch input channel select. the adch bits form a 5-bit field th at selects one of the input channels. the input channels are detailed in table 10-4 . the successive approximation converter subsystem is turned off when the channel select bits are all set. this feature allows for explicit disabling of the adc and isol ation of the input channel from all sources. terminating continuous conversions this way prevents an additional, single conversion from being performed. it is not necessary to set the channel select bits to all ones to place the adc in a low-power state when continuous conversions are not enabled because the module automatically enters a low-power state when a conversion completes. table 10-4. input channel select adch input select 00000?01111 ad0?15 10000?11011 ad16?27 11100 reserved 11101 v refh 11110 v refl 11111 module disabled
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 141 10.3.2 status and contro l register 2 (adcsc2) the adcsc2 register controls the compare function, convers ion trigger, and conversion active of the adc module. 10.3.3 data result hi gh register (adcrh) in 12-bit operation, adcrh contains the upper four bits of the result of a 12-bit conversion. in 10-bit mode, adcrh contains the upper two bi ts of the result of a 10-bit conversion. when configured for 10-bit mode, adr[11:10] are cleared. when configured for 8-bit mode, adr[11:8] are cleared. in 12-bit and 10-bit mode, adcrh is updated each time a conversi on completes except when automatic compare is enabled and the compare condition is not me t. when a compare event does occur, the value is the addition of the conversion result and the two?s complement of the compare value. in 12-bit and 10-bit mode, reading adcrh prevents the adc from transferring s ubsequent conversion resu lts into the result registers until adcrl is read. if ad crl is not read until after the next conversion is completed, the intermediate conversion result is lost. in 8-b it mode, there is no in terlocking with adcrl. 7654 3 210 radact adtrg acfe acfgt 00 r 1 r 1 w r e s e t :0000 0 000 1 bits 1 and 0 are reserved bits that must always be written to 0. figure 10-4. status and control register 2 (adcsc2) table 10-5. adcsc2 register field descriptions field description 7 adact conversion active. indicates that a conversion is in progress. adact is set when a conversion is initiated and cleared when a conversion is completed or aborted. 0 conversion not in progress 1 conversion in progress 6 adtrg conversion trigger select. selects the type of trigger us ed for initiating a conversion. two types of triggers are selectable: software trigger and hardware trigger. when software trigger is selected, a conversion is initiated following a write to adcsc1. when hardware trigger is selected, a conversion is initiated following the assertion of the adhwt input. 0 software trigger selected 1 hardware trigger selected 5 acfe compare function enable. enables the compare function. 0 compare function disabled 1 compare function enabled 4 acfgt compare function greater than enable. configures the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value. the compare function defaults to triggering when the result of the compare of the input being monitored is less than the compare value. 0 compare triggers when input is less than compare value 1 compare triggers when input is greater than or equal to compare value
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 142 freescale semiconductor if the mode bits are changed, a ny data in adcrh becomes invalid. 10.3.4 data result low register (adcrl) adcrl contains the lower eight bits of the result of a 12-bi t or 10-bit conversion, and all eight bits of an 8-bit conversion. this register is updated each time a conversion completes except when automatic compare is enabled and the compar e condition is not met. in 12-bi t and 10-bit mode, reading adcrh prevents the adc from transferring subsequent conversion results into the result registers until adcrl is read. if adcrl is not read until the after next conversion is completed, the intermediate conversion results are lost. in 8-bit mode, there is no interloc king with adcrh. if the m ode bits are changed, any data in adcrl becomes invalid. 10.3.5 compare value high register (adccvh) in 12-bit mode, the adccvh register holds the upper four bits of the 12-bit compare value. when the compare function is enabled, these bi ts are compared to the upper four bits of the result following a conversion in 12-bit mode. in 10-bit mode, the adccvh register holds the upper tw o bits of the 10-bit comp are value (adcv[9:8]). these bits are compared to the upper two bits of the result follow ing a conversion in 10-bit mode when the compare function is enabled. in 8-bit mode, adccvh is not used during compare. 7654 3 210 r 0 0 0 0 adr11 adr10 adr9 adr8 w r e s e t :0000 0 000 figure 10-5. data result high register (adcrh) 7654 3 210 r adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 w r e s e t :0000 0 000 figure 10-6. data resu lt low register (adcrl) 7654 3 210 r0 0 0 0 adcv11 adcv10 adcv9 adcv8 w r e s e t :0000 0 000 figure 10-7. compare value high register (adccvh)
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 143 10.3.6 compare value low register (adccvl) this register holds the lower 8 bits of the 12-bit or 10-bit compare value or all 8 bits of the 8-bit compare value. when the compare function is enabled, bits adcv[7:0] are compared to the lower 8 bits of the result following a conversion in 12-bit, 10-bit or 8-bit mode. 10.3.7 configuration register (adccfg) adccfg selects the mode of operati on, clock source, clock di vide, and configures for low power and long sample time. 7654 3 210 r adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 w reset:0000 0 000 figure 10-8. compare value low register (adccvl) 7654 3 210 r adlpc adiv adlsmp mode adiclk w reset:0000 0 000 figure 10-9. configuration register (adccfg) table 10-6. adccfg regist er field descriptions field description 7 adlpc low-power configuration. adlpc controls the speed an d power configuration of th e successive approximation converter. this optimizes power consumptio n when higher sample rates are not required. 0 high speed configuration 1 low power configuration:the power is reduced at the expense of maximum clock speed. 6:5 adiv clock divide select. adiv selects the divide ratio us ed by the adc to generate the internal clock adck. ta b l e 1 0 - 7 shows the available clock configurations. 4 adlsmp long sample time configuration. adlsmp selects bet ween long and short sample time. this adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if hi gh conversion rates are not required. 0 short sample time 1 long sample time 3:2 mode conversion mode selection. mode bits are used to select between 12-, 10-, or 8-bit operation. see table 10-8 . 1:0 adiclk input clock select. adiclk bits select the input cl ock source to generate the internal clock adck. see ta b l e 1 0 - 9 .
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 144 freescale semiconductor 10.3.8 pin control 1 register (apctl1) the pin control registers di sable the i/o port control of mcu pins used as analog inputs. apctl1 is used to control the pins associated with channels 0?7 of the adc module. table 10-7. clock divide select adiv divide ratio clock rate 00 1 input clock 01 2 input clock 2 10 4 input clock 4 11 8 input clock 8 table 10-8. conversion modes mode mode description 00 8-bit conversion (n=8) 01 12-bit conversion (n=12) 10 10-bit conversion (n=10) 11 reserved table 10-9. input clock select adiclk selected clock source 00 bus clock 01 bus clock divided by 2 10 alternate clock (altclk) 11 asynchronous clock (adack) 7654 3 210 r adpc7 adpc6 adpc5 adpc4 adpc3 adpc2 adpc1 adpc0 w reset:0000 0 000 figure 10-10. pin control 1 register (apctl1) table 10-10. apctl1 register field descriptions field description 7 adpc7 adc pin control 7. adpc7 controls the pin associated with channel ad7. 0 ad7 pin i/o control enabled 1 ad7 pin i/o control disabled 6 adpc6 adc pin control 6. adpc6 controls the pin associated with channel ad6. 0 ad6 pin i/o control enabled 1 ad6 pin i/o control disabled
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 145 10.3.9 pin control 2 register (apctl2) apctl2 controls channels 8?15 of the adc module. 5 adpc5 adc pin control 5. adpc5 controls the pin associated with channel ad5. 0 ad5 pin i/o control enabled 1 ad5 pin i/o control disabled 4 adpc4 adc pin control 4. adpc4 controls the pin associated with channel ad4. 0 ad4 pin i/o control enabled 1 ad4 pin i/o control disabled 3 adpc3 adc pin control 3. adpc3 controls the pin associated with channel ad3. 0 ad3 pin i/o control enabled 1 ad3 pin i/o control disabled 2 adpc2 adc pin control 2. adpc2 controls the pin associated with channel ad2. 0 ad2 pin i/o control enabled 1 ad2 pin i/o control disabled 1 adpc1 adc pin control 1. adpc1 controls the pin associated with channel ad1. 0 ad1 pin i/o control enabled 1 ad1 pin i/o control disabled 0 adpc0 adc pin control 0. adpc0 controls the pin associated with channel ad0. 0 ad0 pin i/o control enabled 1 ad0 pin i/o control disabled 7654 3 210 r adpc15 adpc14 adpc13 adpc12 adpc11 adpc10 adpc9 adpc8 w reset:0000 0 000 figure 10-11. pin control 2 register (apctl2) table 10-11. apctl2 register field descriptions field description 7 adpc15 adc pin control 15. adpc15 controls the pin associated with channel ad15. 0 ad15 pin i/o control enabled 1 ad15 pin i/o control disabled 6 adpc14 adc pin control 14. adpc14 controls the pin associated with channel ad14. 0 ad14 pin i/o control enabled 1 ad14 pin i/o control disabled 5 adpc13 adc pin control 13. adpc13 controls the pin associated with channel ad13. 0 ad13 pin i/o control enabled 1 ad13 pin i/o control disabled table 10-10. apctl1 register field descriptions (continued) field description
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 146 freescale semiconductor 10.3.10 pin control 3 register (apctl3) apctl3 controls channels 16?23 of the adc module. 4 adpc12 adc pin control 12. adpc12 controls the pin associated with channel ad12. 0 ad12 pin i/o control enabled 1 ad12 pin i/o control disabled 3 adpc11 adc pin control 11. adpc11 controls the pin associated with channel ad11. 0 ad11 pin i/o control enabled 1 ad11 pin i/o control disabled 2 adpc10 adc pin control 10. adpc10 controls the pin associated with channel ad10. 0 ad10 pin i/o control enabled 1 ad10 pin i/o control disabled 1 adpc9 adc pin control 9. adpc9 controls the pin associated with channel ad9. 0 ad9 pin i/o control enabled 1 ad9 pin i/o control disabled 0 adpc8 adc pin control 8. adpc8 controls the pin associated with channel ad8. 0 ad8 pin i/o control enabled 1 ad8 pin i/o control disabled 7654 3 210 r adpc23 adpc22 adpc21 adpc20 adpc19 adpc18 adpc17 adpc16 w reset:0000 0 000 figure 10-12. pin control 3 register (apctl3) table 10-12. apctl3 register field descriptions field description 7 adpc23 adc pin control 23. adpc23 controls the pin associated with channel ad23. 0 ad23 pin i/o control enabled 1 ad23 pin i/o control disabled 6 adpc22 adc pin control 22. adpc22 controls the pin associated with channel ad22. 0 ad22 pin i/o control enabled 1 ad22 pin i/o control disabled 5 adpc21 adc pin control 21. adpc21 controls the pin associated with channel ad21. 0 ad21 pin i/o control enabled 1 ad21 pin i/o control disabled 4 adpc20 adc pin control 20. adpc20 controls the pin associated with channel ad20. 0 ad20 pin i/o control enabled 1 ad20 pin i/o control disabled table 10-11. apctl2 register field descriptions (continued) field description
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 147 10.4 functional description the adc module is disabled during re set or when the adch bits are all high. the module is idle when a conversion has completed and another conversion has not been initiated. when idle, the module is in its lowest power state. the adc can perform an analog-to-dig ital conversion on any of the software selectable channels. in 12-bit and 10-bit mode, the selected channel voltage is c onverted by a successive a pproximation algorithm into a 12-bit digital result. in 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a 9-bit digital result. when the conversion is completed, the result is plac ed in the data registers (adcrh and adcrl). in 10-bit mode, the result is rounded to 10 bits and pla ced in the data registers (adcrh and adcrl). in 8-bit mode, the result is rounded to 8 bits and placed in adcrl. the conversion complete flag (coco) is then set and an interrupt is ge nerated if the conversion complete in terrupt has been enabled (aien = 1). the adc module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. the compare f unction is enabled by setting the acfe bit and operates with any of the conversion modes and configurations. 10.4.1 clock select and divide control one of four clock sources can be selected as the cl ock source for the adc module. this clock source is then divided by a configurable valu e to generate the input clock to the converter (adck). the clock is selected from one of the following sources by means of the adiclk bits. ? the bus clock, which is e qual to the frequency at which software is executed. this is the default selection following reset. ? the bus clock divided by two. for higher bus clock rates, this allows a maxi mum divide by 16 of the bus clock. ? altclk, as defined for this mc u (see module section introduction). 3 adpc19 adc pin control 19. adpc19 controls the pin associated with channel ad19. 0 ad19 pin i/o control enabled 1 ad19 pin i/o control disabled 2 adpc18 adc pin control 18. adpc18 controls the pin associated with channel ad18. 0 ad18 pin i/o control enabled 1 ad18 pin i/o control disabled 1 adpc17 adc pin control 17. adpc17 controls the pin associated with channel ad17. 0 ad17 pin i/o control enabled 1 ad17 pin i/o control disabled 0 adpc16 adc pin control 16. adpc16 controls the pin associated with channel ad16. 0 ad16 pin i/o control enabled 1 ad16 pin i/o control disabled table 10-12. apctl3 register field descriptions (continued) field description
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 148 freescale semiconductor ? the asynchronous clock (adack). this clock is ge nerated from a clock source within the adc module. when selected as the clock source, this clock remains active while the mcu is in wait or stop3 mode and allows conversions in these modes for lower noise operation. whichever clock is selecte d, its frequency must fall within the specified freque ncy range for adck. if the available clocks are too sl ow, the adc do not perform according to specifications. if th e available clocks are too fast, the clock must be divided to the appropr iate frequency. this divide r is specified by the adiv bits and can be divide-by 1, 2, 4, or 8. 10.4.2 input select and pin control the pin control registers (apctl3, apctl2, and apctl1) disa ble the i/o port control of the pins used as analog inputs.when a pin control register bit is set, the following conditions are forced for the associated mcu pin: ? the output buffer is forced to its high impedance state. ? the input buffer is disabled. a read of the i/o port returns a zero for any pin with its input buffer disabled. ? the pullup is disabled. 10.4.3 hardware trigger the adc module has a selectable asynchronous hardware conversion trigger, adhwt, that is enabled when the adtrg bit is set. this source is not available on all mcus . consult the module introduction for information on the adhwt sour ce specific to this mcu. when adhwt source is available and hardware trigger is enabled (adt rg=1), a conversion is initiated on the rising edge of adhwt. if a conversion is in progr ess when a rising edge oc curs, the rising edge is ignored. in continuous convert confi guration, only the initial rising edge to launch continuous conversions is observed. the hardware trigger function operates in conjunction with any of the conversion modes and configurations. 10.4.4 conversion control conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined by the mode bits. conversions can be in itiated by a software or ha rdware trigger. in addi tion, the adc module can be configured for low power operation, long sample time, continuous conve rsion, and automatic compare of the conversion result to a soft ware determined compare value. 10.4.4.1 initiating conversions a conversion is initiated: ? following a write to adcsc1 (wit h adch bits not all 1s) if so ftware triggered operation is selected. ? following a hardware trigger (adhwt) event if hardware triggered operation is selected. ? following the transfer of the result to the data registers when continuous conversion is enabled.
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 149 if continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion. in software triggered operation, continuous conversions begin after adcsc1 is written and continue until aborted. in hardware triggered operation, continuous conversions begin after a hardware trigger event a nd continue until aborted. 10.4.4.2 completing conversions a conversion is completed when the result of the convers ion is transferred into th e data result registers, adcrh and adcrl. this is indicated by the setting of coco. an interr upt is generated if aien is high at the time that coco is set. a blocking mechanism prevents a new result from overwriting previous data in adcrh and adcrl if the previous data is in the process of being read wh ile in 12-bit or 10-bit mode (the adcrh register has been read but the adcrl register ha s not). when blocking is active, the data transfer is blocked, coco is not set, and the new result is lost. in the case of single conversions with the compare function enabled and the compare condition false, bloc king has no effect and ad c operation is terminate d. in all other cases of operation, when a data transfer is blocked, another convers ion is initiated regardless of the state of adco (single or continuous conversions enabled). if single conversions are enabled, the blocking mechanism could result in several discarded conversions and excess power consumption. to avoid this issue, the data registers must not be read after initiating a single conversion until the conversion completes. 10.4.4.3 aborting conversions any conversion in progress is aborted when: ? a write to adcsc1 occurs (the current convers ion will be aborted and a new conversion will be initiated, if adch are not all 1s). ? a write to adcsc2, adccfg, adccvh, or adccvl occurs. this indicates a mode of operation change has occurred and the current conversion is therefore invalid. ? the mcu is reset. ? the mcu enters stop mode with adack not enabled. when a conversion is aborted, the contents of the data registers, adcrh and adcrl, are not altered. however, they continue to be the values transferred after the completion of the last successful conversion. if the conversion was aborted by a reset, adcrh and adcrl return to their reset states. 10.4.4.4 power control the adc module remains in its idle st ate until a convers ion is initiated. if adack is selected as the conversion clock source, the adack clock generator is also enabled. power consumption when active can be reduced by se tting adlpc. this results in a lower maximum value for f adck (see the electrical specifications).
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 150 freescale semiconductor 10.4.4.5 sample time and total conversion time the total conversion time depends on the sample time (as determined by adlsmp), the mcu bus frequency, the conversion mode (8-bit, 10-bit or 12- bit), and the frequency of the conversion clock ( f adck ). after the module becomes active, sampling of the input begins. adlsmp sele cts between short (3.5 adck cycles) and long (23.5 adck cycles) sample time s.when sampling is complete, the converter is isolated from the input channel and a successive approximation algorith m is performed to determine the digital value of the analog signal. the result of the conversion is transferred to adcrh and adcrl upon completion of the conversion algorithm. if the bus frequency is less than the f adck frequency, precise sample ti me for continuous conversions cannot be guaranteed when s hort sample is enabled (a dlsmp=0). if the bus freque ncy is less than 1/11th of the f adck frequency, precise sample ti me for continuous conversions cannot be guaranteed when long sample is enabled (adlsmp=1). the maximum total conversion time for di fferent conditions is summarized in table 10-13 . the maximum total conversion time is determined by the clock source chosen and th e divide ratio selected. the clock source is selectable by th e adiclk bits, and the divide ratio is specified by the adiv bits. for example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 mhz, th en the conversion time for a single conversion is: table 10-13. total conversion time vs. control conditions conversion type adiclk adlsmp m ax total conversion time single or first continuous 8-bit 0x, 10 0 20 adck cycles + 5 bus clock cycles single or first continuous 10 -bit or 12-bit 0x, 10 0 23 adck cycles + 5 bus clock cycles single or first continuous 8-bit 0x, 10 1 40 adck cycles + 5 bus clock cycles single or first continuous 10 -bit or 12-bit 0x, 10 1 43 adck cycles + 5 bus clock cycles single or first continuous 8-bit 11 0 5 s + 20 adck + 5 bus clock cycles single or first continuous 10-bit or 12-bit 11 0 5 s + 23 adck + 5 bus clock cycles single or first continuous 8-bit 11 1 5 s + 40 adck + 5 bus clock cycles single or first continuous 10-bit or 12-bit 11 1 5 s + 43 adck + 5 bus clock cycles subsequent continuous 8-bit; f bus > f adck xx 0 17 adck cycles subsequent continuous 10-bit or 12-bit; f bus > f adck xx 0 20 adck cycles subsequent continuous 8-bit; f bus > f adck /11 xx 1 37 adck cycles subsequent continuous 10-bit or 12-bit; f bus > f adck /11 xx 1 40 adck cycles 23 adck cyc conversion time = 8 mhz/1 number of bus cycles = 3.5 s x 8 mhz = 28 cycles 5 bus cyc 8 mhz + = 3.5 s
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 151 note the adck frequency must be between f adck minimum and f adck maximum to meet adc specifications. 10.4.5 automatic compare function the compare function can be configured to check for an upper or lower limit. after the input is sampled and converted, the result is added to the two? s complement of the compare value (adccvh and adccvl). when comparing to an upper limit (acfgt = 1), if the result is greater-than or equal-to the compare value, coco is set. when comparing to a lower limit (acfgt = 0), if the result is less than the compare value, coco is set. the value generated by the addition of the conversion result and the two?s complement of the compare value is transferred to adcrh and adcrl. upon completion of a conversion while the compare f unction is enabled, if the compare condition is not true, coco is not set and no data is transferred to the result register s. an adc interrupt is generated upon the setting of coco if the adc interrupt is enabled (aien = 1). note the compare function can monitor the voltage on a channel while the mcu is in wait or stop3 mode. the adc interrupt wakes the mcu when the compare condition is met. 10.4.6 mcu wait mode operation wait mode is a lower power-consumption standby mode from which recovery is fast because the clock sources remain active. if a conversion is in progress when the mcu enters wait mode, it continues until completion. conversions can be initiated while the mcu is in wait mode by means of the hardware trigger or if continuous conversions are enabled. the bus clock, bus clock divided by two, and adack are available as conversion clock sources while in wait mode. the use of altclk as the conversion cloc k source in wait is depe ndent on the definition of altclk for this mcu. consult the module introduct ion for information on altclk specific to this mcu. a conversion complete event sets the coco and genera tes an adc interrupt to wake the mcu from wait mode if the adc interrupt is enabled (aien = 1). 10.4.7 mcu stop3 mode operation stop mode is a low power-consumpti on standby mode during which most or all clock so urces on the mcu are disabled. 10.4.7.1 stop3 mode with adack disabled if the asynchronous clock, adack, is not selected as the conversion cl ock, executing a stop instruction aborts the current conversion and places the adc in its idle state. the contents of adcrh and adcrl
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 152 freescale semiconductor are unaffected by stop3 mode. after exiting from stop3 m ode, a software or hardware trigger is required to resume conversions. 10.4.7.2 stop3 mode with adack enabled if adack is selected as the conversion clock, the adc conti nues operation during stop3 mode. for guaranteed adc operation, the mcu?s voltage regulator must remain active during stop3 mode. consult the module introduction for configur ation information for this mcu. if a conversion is in progress when the mcu enters stop3 mode, it cont inues until completion. conversions can be initiated while the mcu is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. a conversion complete event sets the coco and gene rates an adc interrupt to wake the mcu from stop3 mode if the adc interrupt is enabled (aien = 1). note the adc module can wake the system from low-power stop and cause the mcu to begin consuming run-level currents without generating a system level interrupt. to prevent this scenario, software must ensure the data transfer blocking mechanism (discussed in section 10.4.4.2, ?completing conversions ,?) is cleared when entering stop3 and continuing adc conversions. 10.4.8 mcu stop2 mode operation the adc module is automatically disabled when the mcu enters stop2 mode . all module registers contain their reset values follow ing exit from stop2. therefore, the module must be re-enabled and re-configured following exit from stop2. 10.5 initialization information this section gives an example that provides some ba sic direction on how to in itialize and configure the adc module. you can configure the module for 8-, 10-, or 12-bit resolution, single or continuous conversion, and a polled or interrupt appr oach, among many other options. refer to table 10-7 , table 10-8 , and table 10-9 for information used in this example. note hexadecimal values designated by a pr eceding 0x, binary values designated by a preceding %, and decimal va lues have no preceding character.
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 153 10.5.1 adc module in itialization example 10.5.1.1 initialization sequence before the adc module can be used to complete conversions, an initialization procedure must be performed. a typical sequence is as follows: 1. update the configuration register (adccfg) to select the input clock source and the divide ratio used to generate the internal cloc k, adck. this register is also used for sele cting sample time and low-power configuration. 2. update status and control regi ster 2 (adcsc2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. update status and control regist er 1 (adcsc1) to select whethe r conversions will be continuous or completed only once, and to en able or disable conversion comple te interrupts. the input channel on which conversions will be performed is also selected here. 10.5.1.2 pseudo-code example in this example, the adc module is set up with interrupts enabled to perfor m a single 10-bit conversion at low power with a long sample tim e on input channel 1, where the intern al adck clock is derived from the bus clock divided by 1. adccfg = 0x98 (%10011000) bit 7 adlpc 1 configures for low power (lowers maximum clock speed) bit 6:5 adiv 00 sets the adck to the input clock 1 bit 4 adlsmp 1 configures for long sample time bit 3:2 mode 10 sets mode at 10-bit conversions bit 1:0 adiclk 00 selects bus clock as input clock source adcsc2 = 0x00 (%00000000) bit 7 adact 0 flag indicates if a conversion is in progress bit 6 adtrg 0 software trigger selected bit 5 acfe 0 compare function disabled bit 4 acfgt 0 not used in this example bit 3:2 00 reserved, always reads zero bit 1:0 00 reserved for freescale?s internal use; always write zero adcsc1 = 0x41 (%01000001) bit 7 coco 0 read-only flag which is set when a conversion completes bit 6 aien 1 conversion complete interrupt enabled bit 5 adco 0 one conversion only (continuous conversions disabled) bit 4:0 adch 00001 input channel 1 selected as adc input channel adcrh/l = 0xxx holds results of conversion. read high byte (adcrh) before low byte (adcrl) so that conversion data cannot be overwritten with data from the next conversion. adccvh/l = 0xxx holds compare value when compare function enabled
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 154 freescale semiconductor apctl1=0x02 ad1 pin i/o control disabled. all other ad pins remain general purpose i/o pins apctl2=0x00 all other ad pins remain general purpose i/o pins figure 10-13. initialization flowchart for example 10.6 application information this section contains information for using the adc module in applic ations. the adc has been designed to be integrated into a microcontroller for use in embedded cont rol applications requiring an a/d converter. 10.6.1 external pins and routing the following sections discuss the external pins as sociated with the adc module and how they must be used for best results. 10.6.1.1 analog supply pins the adc module has analog power and ground supplies (v ddad and v ssad ) available as separate pins on some devices. v ssad is shared on the same pin as the mcu digital v ss on some devices. on other ye s no reset initialize adc adccfg = 0x98 adcsc1 = 0x41 adcsc2 = 0x00 check coco=1? read adcrh then adcrl to clear coco bit continue
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 155 devices, v ssad and v ddad are shared with the mcu di gital supply pins. in these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding di gital supply so that some degree of isolation between the supplies is maintained. when available on a separate pin, both v ddad and v ssad must be connected to th e same voltage potential as their corresponding mcu digital supply (v dd and v ss ) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. if separate power supplies are us ed for analog and digital power, th e ground connection between these supplies must be at the v ssad pin. this must be the only ground connection between these supplies if possible. the v ssad pin makes a good single point ground location. 10.6.1.2 analog reference pins in addition to the analog supplies, the adc module ha s connections for two reference voltage inputs. the high reference is v refh , which may be shared on the same pin as v ddad on some devices. the low reference is v refl , which may be shared on the same pin as v ssad on some devices. when available on a separate pin, v refh may be connected to the same potential as v ddad , or may be driven by an external source between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). when available on a separate pin, v refl must be connected to the same voltage potential as v ssad . v refh and v refl must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. ac current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the v refh and v refl loop. the best external component to meet this current dema nd is a 0.1 f capacitor with good high fre quency characteristics. this capacitor is connected between v refh and v refl and must be placed as ne ar as possible to the packag e pins. resistance in the path is not recommended because th e current causes a voltage drop that could result in conversion errors. inductance in this path must be minimum (parasitic only). 10.6.1.3 analog input pins the external analog inputs ar e typically shared with di gital i/o pins on mcu devi ces. the pin i/o control is disabled by setting the appropriate control bit in one of the pin cont rol registers. conversions can be performed on inputs without the associated pin control register bit set. it is recommended that the pin control register bit always be set when using a pin as an analog i nput. this avoids problems with contention because the output buffer is in its high impedance st ate and the pullup is disabled. also, the input buffer draws dc current when its input is not at v dd or v ss . setting the pin control regist er bits for all pins used as analog inputs must be done to achieve lowest operating current. empirical data shows that capacito rs on the analog inputs improve perfor mance in the presence of noise or when the source impeda nce is high. use of 0.01 f capacitors with good high-frequency characteristics is sufficient. these capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to v ssa . for proper conversion, the input voltage must fall between v refh and v refl . if the input is equal to or exceeds v refh , the converter circuit converts the signal to 0xfff (full scale 12-bit representation), 0x3ff (full scale 10-bit representa tion) or 0xff (full scale 8-bit representa tion). if the input is equal to or less
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 156 freescale semiconductor than v refl , the converter circuit converts it to 0x000. input voltages between v refh and v refl are straight-line linear conversions. there is a brief current associated with v refl when the sampling capacitor is charging. the input is sampled for 3.5 cy cles of the adck source when adlsmp is low, or 23.5 cycles when adlsmp is high. for minimal loss of accuracy due to current injection, pi ns adjacent to the analog input pins must not be transitioning during conversions. 10.6.2 sources of error several sources of error exist for a/d conversions. these are discussed in the following sections. 10.6.2.1 sampling error for proper conversions, the input mu st be sampled long eno ugh to achieve the prope r accuracy. given the maximum input resistance of approximately 7k and input capacitance of a pproximately 5.5 pf, sampling to within 1/4 lsb (at 12-bit resolution) can be achieved with in the minimum sample window (3.5 cycles @ 8 mhz maximum adck frequency) provided the re sistance of the external analog source (r as ) is kept below 2 k . higher source resistances or higher-accuracy sampli ng is possible by setting adlsmp (to increase the sample window to 23.5 cycles) or decreasing adck frequency to increase sample time. 10.6.2.2 pin leakage error leakage on the i/o pins can cause conversion erro r if the external analog source resistance (r as ) is high. if this error cannot be tolera ted by the application, keep r as lower than v ddad /(2 n *i leak ) for less than 1/4 lsb leakage error (n = 8 in 8-bit, 10 in 10-bit or 12 in 12-bit mode). 10.6.2.3 noise-induced errors system noise that occurs during the sample or c onversion process can affect the accuracy of the conversion. the adc accuracy numbers are guaranteed as specified only if the following conditions are met: ? there is a 0.1 f low-esr capacitor from v refh to v refl . ? there is a 0.1 f low-esr capacitor from v ddad to v ssad . ? if inductive isolation is used from the primary supply, an additional 1 f capacitor is placed from v ddad to v ssad . ?v ssad (and v refl , if connected) is connected to v ss at a quiet point in the ground plane. ? operate the mcu in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the adc conversion. ? for software triggered convers ions, immediately follow the write to adcsc1 with a wait instruction or stop instruction. ? for stop3 mode operation, select adack as th e clock source. operation in stop3 reduces v dd noise but increases effective conve rsion time due to stop recovery.
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 157 ? there is no i/o switching, input or output, on the mcu during the conversion. there are some situations where ex ternal system activity causes radiat ed or conducted noi se emissions or excessive v dd noise is coupled into the adc. in these situ ations, or when the mcu cannot be placed in wait or stop3 or i/o activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: ? place a 0.01 f capacitor (c as ) on the selected input channel to v refl or v ssad (this improves noise issues, but affects the sample rate ba sed on the external analog source resistance). ? average the result by converti ng the analog input many times in succession and dividing the sum of the results. four samples are requi red to eliminate the effect of a 1 lsb , one-time error. ? reduce the effect of synchronous noise by ope rating off the asynchronous clock (adack) and averaging. noise that is synchronous to adck cannot be averaged out. 10.6.2.4 code width and quantization error the adc quantizes the ideal straight-line transfer function into 4096 steps (in 12-bit mode). each step ideally has the same height (1 code) and width. the width is defined as the de lta between the transition points to one code and the next. the ideal code width for an n bit convert er (in this case n can be 8, 10 or 12), defined as 1 lsb , is: 1 lsb = (v refh ? v refl ) / 2 n eqn. 10-2 there is an inherent quantization e rror due to the digitizati on of the result. for 8-bit or 10-bit conversions the code transitions when the voltage is at the midpoint between the points where th e straight line transfer function is exactly represented by the actual transfer function. therefore, the quantization error will be 1/2 lsb in 8- or 10-bit mode. as a consequence, however, the code wi dth of the first (0x000) conversion is only 1/2 lsb and the code width of the last (0xff or 0x3ff) is 1.5 lsb. for 12-bit conversions the code transitions only after the full code width is present, so the quantization error is ? 1 lsb to 0 lsb and the code width of each step is 1 lsb. 10.6.2.5 linearity errors the adc may also exhibit non-linearity of several forms. every effort has been made to reduce these errors but the system must be aw are of them because they affect overall accuracy. these errors are: ? zero-scale error (e zs ) (sometimes called offset ) ? this error is defined as the difference between the actual code width of the first conversion and th e ideal code width (1/2 lsb in 8-bit or 10-bit modes and 1 lsb in 12-bit mode). if the first conversion is 0x001, th e difference between the actual 0x001 code width and its ideal (1 lsb) is used. ? full-scale error (e fs ) ? this error is defined as the difference between the actual code width of the last conversion and the ideal code widt h (1.5 lsb in 8-bit or 10-bit modes and 1 lsb in 12-bit mode). if the last conversion is 0x3fe, the difference between th e actual 0x3fe code width and its ideal (1 lsb ) is used. ? differential non-linearity (dnl) ? this error is de fined as the worst-case difference between the actual code width and the ideal code width for all conversions.
analog-to-digital converter (s08adc12v1) MC9S08JM16 series data sheet, rev. 2 158 freescale semiconductor ? integral non-linearity (inl) ? this error is defined as the highest-val ue the (absolute value of the) running sum of dnl achieves. more simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. ? total unadjusted error (tue) ? this error is defi ned as the difference between the actual transfer function and the ideal straight-line transfer function and includes all forms of error. 10.6.2.6 code jitter, non-monotonicity, and missing codes analog-to-digital converters are susceptible to thr ee special forms of error. these are code jitter, non-monotonicity, and missing codes. code jitter is when, at certain poi nts, a given input voltage converts to one of two values when sampled repeatedly. ideally, when the input voltage is infinitesi mally smaller than the transition voltage, the converter yields the lower code (a nd vice-versa). however, even small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages ar ound the transition voltage. this range is normally around 1/2 lsb in 8- bit or 10-bit mode, or around 2 lsb in 12-bit mode, and increases with noise. this error may be reduced by repeatedly sampling th e input and averaging the result. additionally the techniques discussed in section 10.6.2.3 reduces this error. non-monotonicity is defined as when, except for code jitter, the convert er converts to a lower code for a higher input voltage. missing codes are those va lues never converted for any input value. in 8-bit or 10-bit mode, the adc is guaranteed to be monotonic and have no missing codes.
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 159 chapter 11 inter-integrated circuit (s08iicv2) 11.1 introduction the MC9S08JM16 series of microcontrollers have an inter-integrated ci rcuit (iic) module for communication with other inte grated circuits. the two pins associat ed with this module, scl and sda, are shared with ptc0 and ptc1, respectively. note MC9S08JM16 devices operate at a high er voltage range (2.7 v to 5.5 v) and do not include stop1 mode. therefor e, please disregard references to stop1.
chapter 11 inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 160 freescale semiconductor figure 11-1. MC9S08JM16 series block diagram highlighting the iic block and pins ptc1/sda ptc0/scl v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta5, pta0 pte0/txd1 pte1/rxd1 ptd1/adp9/acmp? ptd0/adp8/acmp+ ptc5/rxd2 ptc4 ptc3/txd2 ptc2 port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi1) user flash (in bytes) user ram (in bytes) on-chip ice and debug module (dbg) hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pu llup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. pin contains integrated pullup device. 5. when pin functions as kbi (kbipen = 1) and associated pin is configured to enable the pullup device, kbedgn can be used to reco nfigure the pullup as a pulldown device. 2-channel timer/pwm module (tpm2) ptb5/kbip5/adp5 port b pte5/mosi1 pte4/miso1 pte6/spsck1 pte7/ss1 hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset v ssad v ddad v refh analog-to-digital converter (adc) 4-channel timer/pwm module (tpm1) ptd7 2 ptb4/kbip4/adp4 ptg3/kbip7 ptg2/kbip6 port g 8-channel, 12-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg4/xtal ptg5/extal irq/tpmclk rxd2 txd2 sda scl 6 kbipx kbipx tpmclk spsck1 ss1 miso1 mosi1 tpmclk tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 2 4 usb sie usb endpoint ram full speed usb transceiver usbdp usbdn miso2 ss2 spsck2 mosi2 ptb1/mosi2/adp1 ptb0/miso2/adp0 8-/16-bit real-time counter (rtc) ptb3/ss2 /adp3 ptb2/spsck2/adp2 tpm1chx 3 tpm2ch1 tpm2ch0 2 analog comparator (acmp) system usb 3.3 v voltage regulator v usb33 1024 acmpo acmp+ acmp? ptd2/kbip2/acmpo 8-/16-bit serial peripheral interface module (spi2) mc9s08jm8 = 8,192 MC9S08JM16 = 16,384 v ssosc
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 161 11.1.1 features the iic includes these distinctive features: ? compatible with iic bus standard ? multi-master operation ? software programmable for one of 64 different serial clock frequencies ? software selectable acknowledge bit ? interrupt driven byte-by-byte data transfer ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus busy detection ? general call recognition ? 10-bit address extension 11.1.2 modes of operation a brief description of the iic in th e various mcu modes is given here. ? run mode ? this is the basic mode of operation. to conserve power in th is mode, disable the module. ? wait mode ? the module continues to operate while th e mcu is in wait mode and can provide a wake-up interrupt. ? stop mode ? the iic is inactive in stop3 mode fo r reduced power consumption. the stop instruction does not affect iic register st ates. stop2 resets the register contents. 11.1.3 block diagram figure 11-2 is a block diagram of the iic.
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 162 freescale semiconductor figure 11-2. iic functional block diagram 11.2 external signal description this section describes each user-accessible pin signal. 11.2.1 scl ? serial clock line the bidirectional scl is the serial clock line of the iic system. 11.2.2 sda ? serial data line the bidirectional sda is the serial data line of the iic system. 11.3 register definition this section consists of the iic register descriptions in address order. refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all iic registers. this section refers to registers and control bits only by their names. a input sync in/out data shift register address compare interrupt clock control start stop arbitration control ctrl_reg freq_reg addr_reg status_reg data_reg addr_decode data_mux data bus scl sda address
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 163 freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 iic address register (iica) 11.3.2 iic frequency divider register (iicf) 76543210 r ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 w r e s e t00000000 = unimplemented or reserved figure 11-3. iic address register (iica) table 11-1. iica field descriptions field description 7?1 ad[7:1] slave address. the ad[7:1] field contains the slave address to be used by the iic module. this field is used on the 7-bit address scheme and the lower seven bits of the 10-bit address scheme. 76543210 r mult icr w reset00000000 figure 11-4. iic frequency divider register (iicf)
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 164 freescale semiconductor for example, if the bus speed is 8 m hz, the table below shows the possibl e hold time values with different icr and mult selections to achie ve an iic baud rate of 100kbps. table 11-2. iicf field descriptions field description 7?6 mult iic multiplier factor . the mult bits define the multiplier factor, mu l. this factor, along with the scl divider, generates the iic baud rate. the multiplier factor mu l as defined by the mult bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 reserved 5?0 icr iic clock rate . the icr bits are used to prescale the bus clock for bit rate selection. these bits and the mult bits determine the iic baud rate, the sda hold time, the scl start hold time, and the scl stop hold time. ta b l e 1 1 - 4 provides the scl divider and hold values for corresponding values of the icr. the scl divider multiplied by multiplier factor mul generates iic baud rate. eqn. 11-1 sda hold time is the delay from the falling edge of scl (iic clock) to the changing of sda (iic data). sda hold time = bus period (s) mul sda hold value eqn. 11-2 scl start hold time is the delay from the falling edge of sda (iic data) while scl is high (start condition) to the falling edge of scl (iic clock). scl start hold time = bus period (s) mul scl start hold value eqn. 11-3 scl stop hold time is the delay from the rising edge of scl (iic clock) to the rising edge of sda sda (iic data) while scl is high (stop condition). scl stop hold time = bus period (s) mul scl stop hold value eqn. 11-4 table 11-3. hold time values for 8 mhz bus speed mult icr hold times ( s) sda scl start scl stop 0x2 0x00 3.500 3.000 5.500 0x1 0x07 2.500 4.000 5.250 0x1 0x0b 2.250 4.000 5.250 0x0 0x14 2.125 4.250 5.125 0x0 0x18 1.125 4.750 5.125 iic baud rate bus speed (hz) mul scldivider -------------------------------------------- - =
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 165 table 11-4. iic divider and hold values icr (hex) scl divider sda hold value scl hold (start) value sda hold (stop) value icr (hex) scl divider sda hold value scl hold (start) value scl hold (stop) value 00 20 7 6 11 20 160 17 78 81 01 22 7 7 12 21 192 17 94 97 02 24 8 8 13 22 224 33 110 113 03 26 8 9 14 23 256 33 126 129 04 28 9 10 15 24 288 49 142 145 05 30 9 11 16 25 320 49 158 161 06 34 10 13 18 26 384 65 190 193 07 40 10 16 21 27 480 65 238 241 08 28 7 10 15 28 320 33 158 161 09 32 7 12 17 29 384 33 190 193 0a 36 9 14 19 2a 448 65 222 225 0b 40 9 16 21 2b 512 65 254 257 0c 44 11 18 23 2c 576 97 286 289 0d 48 11 20 25 2d 640 97 318 321 0e 56 13 24 29 2e 768 129 382 385 0f 68 13 30 35 2f 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129 446 449 13 72 13 30 37 33 1024 129 510 513 14 80 17 34 41 34 1152 193 574 577 15 88 17 38 45 35 1280 193 638 641 16 104 21 46 53 36 1536 257 766 769 17 128 21 58 65 37 1920 257 958 961 18 80 9 38 41 38 1280 129 638 641 19 96 9 46 49 39 1536 129 766 769 1a 112 17 54 57 3a 1792 257 894 897 1b 128 17 62 65 3b 2048 257 1022 1025 1c 144 25 70 73 3c 2304 385 1150 1153 1d 160 25 78 81 3d 2560 385 1278 1281 1e 192 33 94 97 3e 3072 513 1534 1537 1f 240 33 118 121 3f 3840 513 1918 1921
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 166 freescale semiconductor 11.3.3 iic control register (iicc1) 11.3.4 iic status register (iics) 76543210 r iicen iicie mst tx txak 000 w rsta r e s e t00000000 = unimplemented or reserved figure 11-5. iic control register (iicc1) table 11-5. iicc1 field descriptions field description 7 iicen iic enable. the iicen bit determines whether the iic module is enabled. 0 iic is not enabled 1 iic is enabled 6 iicie iic interrupt enable. the iicie bit determines whether an iic interrupt is requested. 0 iic interrupt request not enabled 1 iic interrupt request enabled 5 mst master mode select. the mst bit changes from a 0 to a 1 when a start signal is generated on the bus and master mode is selected. when this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 0slave mode 1 master mode 4 tx transmit mode select. the tx bit selects the direction of master and slave transfers. in master mode, this bit must be set according to the type of tr ansfer required. th erefore, for address cycles, this bit is always high. when addressed as a slave, this bit must be set by software according to the srw bit in the status register. 0 receive 1 transmit 3 txak transmit acknowledge enable. this bit specifies the value driven onto the sda during data acknowledge cycles for master and slave receivers. 0 an acknowledge signal is sent out to the bus after receiving one data byte 1 no acknowledge signal response is sent 2 rsta repeat start. writing a 1 to this bit generates a repeated start condition provided it is the current master. this bit is always read as cleared. attempting a repeat at the wrong time results in loss of arbitration. 76543210 rtcf iaas busy arbl 0srw iicif rxak w r e s e t10000000 = unimplemented or reserved figure 11-6. iic status register (iics)
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 167 11.3.5 iic data i/o register (iicd) table 11-6. iics field descriptions field description 7 tcf transfer complete flag. this bit is set on the completion of a byte transfer. this bit is only valid during or immediately following a transfer to the iic module or from the iic module.the tcf bit is cleared by reading the iicd register in receive mode or writing to the iicd in transmit mode. 0 transfer in progress 1 transfer complete 6 iaas addressed as a slave. the iaas bit is set when the calling address matches the programmed slave address or when the gcaen bit is set and a general call is received. writing the iicc register clears this bit. 0 not addressed 1 addressed as a slave 5 busy bus busy. the busy bit indicates the status of the bus regardl ess of slave or master mode. the busy bit is set when a start signal is detected and cleared when a stop signal is detected. 0 bus is idle 1bus is busy 4 arbl arbitration lost. this bit is set by hardware when the arbitration procedure is lost. the arbl bit must be cleared by software by writing a 1 to it. 0 standard bus operation 1 loss of arbitration 2 srw slave read/write. when addressed as a slave, the srw bit indica tes the value of the r/w command bit of the calling address sent to the master. 0 slave receive, master writing to slave 1 slave transmit, master reading from slave 1 iicif iic interrupt flag. the iicif bit is set when an interrupt is pendi ng. this bit must be cleared by software, by writing a 1 to it in the interrupt routine. o ne of the following events can set the iicif bit: ? one byte transfer completes ? match of slave address to calling address ? arbitration lost 0 no interrupt pending 1 interrupt pending 0 rxak receive acknowledge . when the rxak bit is low, it indicates an acknowledge signal has been received after the completion of one byte of data transmission on the bus. if the rxak bit is high it means that no acknowledge signal is detected. 0 acknowledge received 1 no acknowledge received 76543210 r data w r e s e t00000000 figure 11-7. iic data i/o register (iicd)
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 168 freescale semiconductor note when transitioning out of master r eceive mode, the iic mode must be switched before reading the iicd register to prevent an inadvertent initiation of a master receive data transfer. in slave mode, the same functions are avai lable after an addres s match has occurred. the tx bit in iicc must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. for instance, if the iic is c onfigured for master transmit but a master receive is desired, reading the iicd does not initiate the receive. reading the iicd returns the last byte received while the iic is configured in master receive or slave receive modes. the iicd does not reflect every byte transmitted on the iic bus, nor can software verify that a byte has been written to the iicd correctly by reading it back. in master transmit mode, th e first byte of data written to iicd foll owing assertion of ms t is used for the address transfer and must comprise of the calling address (in bit 7 to bi t 1) concatenated with the required r/w bit (in position bit 0). 11.3.6 iic control register 2 (iicc2) table 11-7. iicd field descriptions field description 7?0 data data ? in master transmit mode, when data is written to t he iicd, a data transfer is init iated. the most significant bit is sent first. in master receive mode, reading this register initiates receiving of the ne xt byte of data. 76543210 r gcaen adext 000 ad10 ad9 ad8 w r e s e t00000000 = unimplemented or reserved figure 11-8. iic control register (iicc2) table 11-8. iicc2 field descriptions field description 7 gcaen general call address enable. the gcaen bit enables or disables general call address. 0 general call address is disabled 1 general call address is enabled 6 adext address extension. the adext bit controls the number of bits used for the slave address. 0 7-bit address scheme 1 10-bit address scheme 2?0 ad[10:8] slave address. the ad[10:8] field contains the upper three bits of the slave address in the 10-bit address scheme. this field is only valid when the adext bit is set.
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 169 11.4 functional description this section provides a complete func tional description of the iic module. 11.4.1 iic protocol the iic bus system uses a serial data line (sda) and a serial clock line (scl) for da ta transfer. all devices connected to it must have open drain or open collec tor outputs. a logic and function is exercised on both lines with external pullup resistors. the value of these resistors is system dependent. normally, a standard communication is composed of four parts: ? start signal ? slave address transmission ? data transfer ? stop signal the stop signal must not be confused with the cpu stop instruc tion. the iic bus system communication is described briefly in the follow ing sections and illustrated in figure 11-9 . figure 11-9. iic bus transmission signals 11.4.1.1 start signal when the bus is free, no master de vice is engaging the bus (scl and sda lines are at logical high), a master may initiate communication by se nding a start signal. as shown in figure 11-9, a start signal is defined as a high-to-low transition of sda while scl is high. this si gnal denotes the beginning of a new data transfer (each data transfer ma y contain several bytes of data) and br ings all slaves out of their idle states. scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 12 5 678 msb lsb repeated 34 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 170 freescale semiconductor 11.4.1.2 slave address transmission the first byte of data transferred im mediately after the start signal is th e slave address transmitted by the master. this is a seven-bit ca lling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer, the slave transmits data to the master. 0 = write transfer, the master transmits data to the slave. only the slave with a calling addr ess that matches the one transmitt ed by the master responds by sending back an acknowledge bit. this is done by pul ling the sda low at the ninth clock (see figure 11-9 ). no two slaves in the system may have the same a ddress. if the iic module is the master, it must not transmit an address equal to its own slave address. the iic cannot be ma ster and slave at the same time. however, if arbitration is lost during an address cycle, the iic reverts to slave mode and operates correctly even if it is being a ddressed by another master. 11.4.1.3 data transfer before successful slave addressing is achieved, the da ta transfer can proceed byte-by-byte in a direction specified by the r/w bit sent by the calling master. all transfers that come after an addres s cycle are referred to as data transf ers, even if they carry sub-address information for the slave device each data byte is 8 bits long. data may be changed only while scl is lo w and must be held stable while scl is high as shown in figure 11-9 . there is one clock pulse on scl for each data bit, the msb being transferred first. each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. an acknowledge is signalled by pulling the sda low at th e ninth clock. in summary, one complete data transfer needs nine clock pulses. if the slave receiver does not acknowledge the master in the ninth bit time, the sda line must be left high by the slave. the master interprets the failed acknowledge as an unsu ccessful data transfer. if the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the sda line. in either case, the data transfer is abor ted and the master does one of two things: ? relinquishes the bus by generating a stop signal. ? commences a new calling by gene rating a repeated start signal. 11.4.1.4 stop signal the master can terminate the comm unication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a ca lling command without gene rating a stop signal first. this is called repeated start. a stop signal is defined as a low-to-h igh transition of sda while scl at logical 1 (see figure 11-9 ). the master can generate a stop even if the slave ha s generated an acknowledge at which point the slave must release the bus.
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 171 11.4.1.5 repeated start signal as shown in figure 11-9 , a repeated start signal is a start signa l generated without first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (tra nsmit/receive mode) wit hout releasing the bus. 11.4.1.6 arbitration procedure the iic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a cl ock synchronization proce dure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. the relative priority of the c ontending masters is determin ed by a data arbitration procedure, a bus master lose s arbitration if it transm its logic 1 while another ma ster transmits logic 0. the losing masters immediately switch ove r to slave receive mode and stop driving sda output. in this case, the transition from master to slave mode does not ge nerate a stop condition. meanwh ile, a status bit is set by hardware to indicate loss of arbitration. 11.4.1.7 clock synchronization because wire-and logic is performed on the scl line, a high-to-low transition on the scl line affects all the devices connected on the bus. th e devices start counting their low pe riod and after a device?s clock has gone low, it holds the scl line lo w until the clock high state is reache d. however, the change of low to high in this device clock may not cha nge the state of the scl line if anot her device clock is still within its low period. therefore, synchronized clock scl is he ld low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 11-10 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the de vice clocks and the state of the scl line and all the devices start counting their high peri ods. the first device to complete its high period pulls the scl line low again. figure 11-10. iic clock synchronization scl1 scl2 scl internal counter reset delay start counting high period
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 172 freescale semiconductor 11.4.1.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hold the scl low after completion of one byt e transfer (9 bits). in such a ca se, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 11.4.1.9 clock stretching the clock synchronization mechanism ca n be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low the slave can drive sc l low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 11.4.2 10-bit address for 10-bit addressing, 0x11110 is used fo r the first 5 bits of the first addr ess byte. various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 11.4.2.1 master-transmitter addresses a slave-receiver the transfer direction is not changed (see table 11-9 ). when a 10-bit address follows a start condition, each slave compares the first seven bits of the fi rst byte of the slave address (11110xx) with its own address and tests whet her the eighth bit (r/w direction bit) is 0. more than one device can find a match and generate an acknowledge (a1). then, each slave that finds a matc h compares the eight bits of the second byte of the slave a ddress with its own addre ss. only one slave finds a match and generates an acknowledge (a2). the matchi ng slave remains addressed by the mast er until it receives a stop condition (p) or a repeated start condition (sr) followed by a different slave address. after the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an iic interrupt. software must ensure the contents of iicd are ignored and not treated as valid data for this interrupt. 11.4.2.2 master-receiver addr esses a slave-transmitter the transfer direction is changed after the second r/w bit (see table 11-10 ). up to and including acknowledge bit a2, the pro cedure is the same as th at described for a master-transmitter addressing a slave-receiver. after the repeated start condition (sr), a matching slav e remembers that it was addressed before. this slave then checks whether the first seven bits of the first byte of the slave address following sr are the same as they were after the start condition (s) a nd tests whether the eighth (r/w ) bit is 1. if there is a match, the slave considers that it has been addresse d as a transmitter and generates acknowledge a3. the slave-transmitter remains addres sed until it receives a stop condition (p) or a repeated start condition (sr) followed by a different slave address. s slave address 1st 7 bits r/w a1 slave address 2nd byte a2 data a ... data a/a p 11110 + ad10 + ad9 0 ad[8:1] table 11-9. master-transmitter addresses slave-receiver with a 10-bit address
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 173 after a repeated start condition (sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (r/w ) bit. however, none of them are addressed because r/w = 1 (for 10-bit devices) or the 11110xx slave address (for 7-bit devices) does not match. after the master-receiver has sent the first byte of th e 10-bit address, the slav e-transmitter sees an iic interrupt. software must ensure the contents of iicd are ignored and not treated as valid data for this interrupt. 11.4.3 general call address general calls can be requested in 7- bit address or 10-bit addr ess. if the gcaen bit is set, the iic matches the general call address as well as its own slave addres s. when the iic responds to a general call, it acts as a slave-receiver and the iaas bit is set after the address cycl e. software must read the iicd register after the first byte transfer to determine whether the address matche s is its own slave addr ess or a general call. if the value is 00, the match is a ge neral call. if the gcaen bit is clear , the iic ignores any data supplied from a general call address by not issuing an acknowledgement. 11.5 resets the iic is disabled after reset. the iic cannot cause an mcu reset. 11.6 interrupts the iic generates a single interrupt. an interrupt from the iic is gene rated when any of the events in table 11-11 occur, provided the iicie bit is set. the interrupt is driven by bit iicif (of the iic status register) and masked with bit iicie (of the iic control register). the iicif bit must be cleared by software by writing a 1 to it in the interrupt routine. you can determine the interrupt type by reading the status register. 11.6.1 byte transfer interrupt the tcf (transfer complete flag) bit is set at the falling edge of the ni nth clock to indica te the completion of byte transfer. s slave address 1st 7 bits r/w a1 slave address 2nd byte a2 sr slave address 1st 7 bits r/w a3 data a ... data a p 11110 + ad10 + ad9 0 ad[8:1] 11110 + ad10 + ad9 1 table 11-10. master-receiver addresses a slave-transmitter with a 10-bit address table 11-11. interrupt summary interrupt source status flag local enable complete 1-byte transfer tcf iicif iicie match of received calling address iaas iicif iicie arbitration lost arbl iicif iicie
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 174 freescale semiconductor 11.6.2 address detect interrupt when the calling address matches the programmed slav e address (iic address register) or when the gcaen bit is set and a general call is received, the ia as bit in the status register is set. the cpu is interrupted, provided the iicie is set. the cpu must check the srw bit and set its tx mode accordingly. 11.6.3 arbitration lost interrupt the iic is a true mul ti-master bus that allows more than one mast er to be connected on it. if two or more masters try to control the bus at the same time, the relative priority of th e contending masters is determined by a data arbitration procedure. the iic module asserts this interrupt wh en it loses the data arbitration process and the arbl bit in the status register is set. arbitration is lost in th e following circumstances: ? sda sampled as a low when the master drives a high during an address or data transmit cycle. ? sda sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. ? a start cycle is attempted when the bus is busy. ? a repeated start cycle is requested in slave mode. ? a stop condition is detected when the master did not request it. this bit must be cleared by software writing a 1 to it.
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 175 11.7 initialization/application information figure 11-11. iic module quick start module initialization (slave) 1. write: iicc2 ? to enable or disable general call ? to select 10-bit or 7-bit addressing mode 2. write: iica ? to set the slave address 3. write: iicc1 ? to enable iic and interrupts 4. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 5. initialize ram variables used to achieve the routine shown in figure 11-12 module initialization (master) 1. write: iicf ? to set the iic baud rate (examp le provided in this chapter) 2. write: iicc1 ? to enable iic and interrupts 3. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 4. initialize ram variables used to achieve the routine shown in figure 11-12 5. write: iicc1 ? to enable tx 0 iicf iica baud rate = busclk / (2 x mult x (scl divider)) tx txak rsta 0 0 iicc1 iicen iicie mst module configuration arbl 0 srw iicif rxak iics tcf iaas busy module status flags register model ad[7:1] when addressed as a slave (in slave mode), the module responds to this address mult icr iicd data data register; write to transmit iic data read to read iic data 0 ad10 ad9 ad8 iicc2 gcaen adext address configuration 0 0
inter-integrated circuit (s08iicv2) MC9S08JM16 series data sheet, rev. 2 176 freescale semiconductor figure 11-12. typical iic interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to iicd switch to rx mode dummy read from iicd generate stop signal read data from iicd and store set txack =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear arbl iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to iicd set rx mode dummy read from iicd ack from receiver ? tx next byte read data from iicd and store switch to rx mode dummy read from iicd rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n iicif address transfer data transfer (mst = 0) (mst = 0) see note 1 1 if general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). if the received address was a general call address, then the general call must be handled by user software. 2 when 10-bit addressing is used to address a slave, the slave s ees an interrupt following the first byte of the extended address . user software must ensure that for this interrupt, the content s of iicd are ignored and not treated as a valid data transfer see note 2
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 177 chapter 12 multi-purpose clock generator (s08mcgv1) 12.1 introduction the multi-purpose clock generator (mcg) module provides several clock source choices for the mcu, which contains a frequency-locked loop (fll) a nd a phase-locked loop (pll) the module can select either of the fll or pll clocks, or either of the inte rnal or external reference clocks as a source for the mcu system clock. whichever clock source is chosen, it is passed th rough a reduced bus divider which allows a lower output clock frequency to be derived. th e mcg also controls an ex ternal oscill ator (xosc) for the use of a crystal or resonator as the external reference clock. for usb operation on the mc9s08jm60 series, the mcg must be configured for pll engaged external (pee) mode using a crystal in order to achieve an mcgout frequency of 48 mhz.
chapter 12 multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 178 freescale semiconductor figure 12-1. MC9S08JM16 series block diagram highlighting mcg block and pins ptc1/sda ptc0/scl v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta5, pta0 pte0/txd1 pte1/rxd1 ptd1/adp9/acmp? ptd0/adp8/acmp+ ptc5/rxd2 ptc4 ptc3/txd2 ptc2 port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi1) user flash (in bytes) user ram (in bytes) on-chip ice and debug module (dbg) hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pu llup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. pin contains integrated pullup device. 5. when pin functions as kbi (kbipen = 1) and associated pin is configured to enable the pullup device, kbedgn can be used to reco nfigure the pullup as a pulldown device. 2-channel timer/pwm module (tpm2) ptb5/kbip5/adp5 port b pte5/mosi1 pte4/miso1 pte6/spsck1 pte7/ss1 hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset v ssad v ddad v refh analog-to-digital converter (adc) 4-channel timer/pwm module (tpm1) ptd7 2 ptb4/kbip4/adp4 ptg3/kbip7 ptg2/kbip6 port g 8-channel, 12-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg4/xtal ptg5/extal irq/tpmclk rxd2 txd2 sda scl 6 kbipx kbipx tpmclk spsck1 ss1 miso1 mosi1 tpmclk tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 2 4 usb sie usb endpoint ram full speed usb transceiver usbdp usbdn miso2 ss2 spsck2 mosi2 ptb1/mosi2/adp1 ptb0/miso2/adp0 8-/16-bit real-time counter (rtc) ptb3/ss2 /adp3 ptb2/spsck2/adp2 tpm1chx 3 tpm2ch1 tpm2ch0 2 analog comparator (acmp) system usb 3.3 v voltage regulator v usb33 1024 acmpo acmp+ acmp? ptd2/kbip2/acmpo 8-/16-bit serial peripheral interface module (spi2) mc9s08jm8 = 8,192 MC9S08JM16 = 16,384 v ssosc
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 179 12.1.1 features key features of the mcg module are: ? frequency-locked loop (fll) ? 0.2% resolution using internal 32 khz reference ? 2% deviation over voltage and temperat ure using internal 32 khz reference ? internal or external reference can be used to control the fll ? phase-locked loop (pll) ? voltage-controlled oscillator (vco) ? modulo vco frequency divider ? phase/frequency detector ? integrated loop filter ? lock detector with interrupt capability ? internal reference clock ? nine trim bits for accuracy ? can be selected as the clock source for the mcu ? external reference clock ? control for external oscillator ? clock monitor with reset capability ? can be selected as the clock source for the mcu ? reference divider is provided ? clock source selected can be divided down by 1, 2, 4, or 8 ? bdc clock (mcglclk) is provide d as a constant divide by 2 of the dco output whether in an fll or pll mode.
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 180 freescale semiconductor figure 12-2. multi-purpose clock generator (mcg) block diagram dco filter rdiv trim external oscillator irefs (xosc) clks n=0-7 / 2 n n=0-3 / 2 n internal reference clock bdiv 9 mcglclk mcgout mcgirclk erefs range erefsten hgo irefsten mcgerclk lp mcgffclk dcoout fll rdiv_clk pll vdiv /(4,8,12,...,40) vco phase detector charge pump internal filter lock detector lock clock monitor oscinit vcoout multi-purpose clock generator (mcg) lp erclken irclken cme loc / 2 plls lols
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 181 12.1.2 modes of operation there are nine modes of operation for the mcg: ? fll engaged internal (fei) ? fll engaged external (fee) ? fll bypassed internal (fbi) ? fll bypassed external (fbe) ? pll engaged external (pee) ? pll bypassed external (pbe) ? bypassed low power internal (blpi) ? bypassed low power external (blpe) ?stop for details see section 12.4.1, ?operational modes .? 12.2 external signal description there are no mcg signals that connect off chip.
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 182 freescale semiconductor 12.3 register definition 12.3.1 mcg control register 1 (mcgc1) 7 6543210 r clks rdiv irefs irclken irefsten w reset: 0 0 0 0 0 1 0 0 figure 12-3. mcg control register 1 (mcgc1) table 12-1. mcg control regi ster 1 field descriptions field description 7:6 clks clock source select ? selects the system clock source. 00 encoding 0 ? output of fll or pll is selected. 01 encoding 1 ? internal reference clock is selected. 10 encoding 2 ? external reference clock is selected. 11 encoding 3 ? reserved, defaults to 00. 5:3 rdiv reference divider ? selects the amount to divide down the refe rence clock selected by the irefs bit. if the fll is selected, the resulting frequency must be in the range 31.25 khz to 39.0625 khz. if the pll is selected, the resulting frequency must be in the range 1 mhz to 2 mhz. 000 encoding 0 ? divides reference clock by 1 (reset default) 001 encoding 1 ? divides reference clock by 2 010 encoding 2 ? divides reference clock by 4 011 encoding 3 ? divides reference clock by 8 100 encoding 4 ? divides reference clock by 16 101 encoding 5 ? divides reference clock by 32 110 encoding 6 ? divides reference clock by 64 111 encoding 7 ? divides reference clock by 128 2 irefs internal reference select ? selects the reference clock source. 1 internal reference clock selected 0 external reference clock selected 1 irclken internal reference clock enable ? enables the internal reference clock for use as mcgirclk. 1 mcgirclk active 0 mcgirclk inactive 0 irefsten internal reference stop enable ? controls whether or not the internal reference clock remains enabled when the mcg enters stop mode. 1 internal reference clock stays enabled in stop if irclken is set or if mcg is in fei, fbi, or blpi mode before entering stop 0 internal reference clock is disabled in stop
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 183 12.3.2 mcg control register 2 (mcgc2) 7 6543210 r bdiv range hgo lp erefs erclken erefsten w reset:0 1000000 figure 12-4. mcg control register 2 (mcgc2) table 12-2. mcg control regi ster 2 field descriptions field description 7:6 bdiv bus frequency divider ? selects the amount to divide down the cloc k source selected by the clks bits in the mcgc1 register. this controls the bus frequency. 00 encoding 0 ? divides selected clock by 1 01 encoding 1 ? divides selected clock by 2 (reset default) 10 encoding 2 ? divides selected clock by 4 11 encoding 3 ? divides selected clock by 8 5 range frequency range select ? selects the frequency range for the external oscillator or external clock source. 1 high frequency range selected for the external oscillator of 1 mhz to 16 mhz (1 mhz to 40 mhz for external clock source) 0 low frequency range selected for the external oscillator of 32 khz to 100 khz (32 khz to 1 mhz for external clock source) 4 hgo high gain oscillator select ? controls the external oscillator mode of operation. 1 configure external oscillator for high gain operation 0 configure external oscillator for low power operation 3 lp low power select ? controls whether the fll (or pll) is disabled in bypassed modes. 1 fll (or pll) is disabled in bypass modes (lower power) . 0 fll (or pll) is not disabled in bypass modes. 2 erefs external reference select ? selects the source for the external reference clock. 1 oscillator requested 0 external clock source requested 1 erclken external reference enable ? enables the external reference clock for use as mcgerclk. 1 mcgerclk active 0 mcgerclk inactive 0 erefsten external reference stop enable ? controls whether or not the exter nal reference clock remains enabled when the mcg enters stop mode. 1 external reference clock stays enabl ed in stop if erclken is set or if mcg is in fee, fbe, pee, pbe, or blpe mode before entering stop 0 external reference clock is disabled in stop
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 184 freescale semiconductor 12.3.3 mcg trim register (mcgtrm) 7 6543210 r trim w por: 1 0 0 0 0 0 0 0 r e s e t :u uuuuuuu figure 12-5. mcg trim register (mcgtrm) table 12-3. mcg trim register field descriptions field description 7:0 trim mcg trim setting ? controls the internal reference clock frequency by controlling the internal reference clock period. the trim bits are binary weighted (i.e., bit 1 wi ll adjust twice as much as bit 0). increasing the binary value in trim will increase the period, and decreasing the value will decrease the period. an additional fine trim bit is available in mcgsc as the ftrim bit. if a trim[7:0] value stored in nonvolatile memory is to be used, it?s the user?s responsibility to copy that value from the nonvolatile memory location to this register.
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 185 12.3.4 mcg status and control register (mcgsc) 7 6543210 r lols lock pllst irefst clkst oscinit ftrim w por: reset: 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 u figure 12-6. mcg status and control register (mcgsc) table 12-4. mcg status and control register field descriptions field description 7 lols loss of lock status ? this bit is a sticky indication of lock status for the fll or pll. lols is set when lock detection is enabled and after acquiring lock, the fll or pll output frequency has fallen outside the lock exit frequency tolerance, d unl . lolie determines whether an interrupt request is made when set. lols is cleared by reset or by writing a logic 1 to lols when lols is set. writing a logic 0 to lols has no effect. 0 fll or pll has not lost lock since lols was last cleared. 1 fll or pll has lost lock since lols was last cleared. 6 lock lock status ? indicates whether the fll or pll has acquired lock. lock detection is disabled when both the fll and pll are disabled. if the lock status bit is set then changing the value of any of the following bits irefs, plls, rdiv[2:0], trim[7:0] (if in fei or fbi modes), or vdiv[3:0] (if in pbe or pee modes), will cause the lock status bit to clear and stay cleared until the fll or pll has reacquired lock. stop mode entry will also cause the lock status bit to clear and stay cleared until the fll or pll has reacquired lock. entry into blpi or blpe mode will also cause the lock status bit to clear and stay cl eared until the mcg has exited these modes and the fll or pll has reacquired lock. 0 fll or pll is currently unlocked. 1 fll or pll is currently locked. 5 pllst pll select status ? the pllst bit indicates the current source for the plls clock. the pllst bit does not update immediately after a write to the plls bit du e to internal synchronization between clock domains. 0 source of plls clock is fll clock. 1 source of plls clock is pll clock. 4 irefst internal reference status ? the irefst bit indicates the current s ource for the reference clock. the irefst bit does not update immediately after a write to the irefs bit due to internal synchronization between clock domains. 0 source of reference clock is external reference clock (o scillator or external clock source as determined by the erefs bit in the mcgc2 register). 1 source of reference clock is internal reference clock. 3:2 clkst clock mode status ? the clkst bits indicate the current clock mode. the clkst bits do not update immediately after a write to the clks bits due to internal synchronization between clock domains. 00 encoding 0 ? output of fll is selected. 01 encoding 1 ? internal reference clock is selected. 10 encoding 2 ? external reference clock is selected. 11 encoding 3 ? output of pll is selected.
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 186 freescale semiconductor 12.3.5 mcg control register 3 (mcgc3) 1 oscinit osc initialization ? if the external reference clock is selected by erclken or by the mcg being in fee, fbe, pee, pbe, or blpe mode, and if erefs is set, then this bit is set after the initialization cycles of the external oscillator clock have completed. this bit is only clea red when either erefs is cleared or when the mcg is in either fei, fbi, or blpi mode and erclken is cleared. 0 ftrim mcg fine trim ? controls the smallest adjust ment of the internal reference clock frequency. setting ftrim will increase the period and clearing ftrim will decrease the period by the smallest amount possible. if an ftrim value stored in nonvolatile memory is to be used , it?s the user?s responsibili ty to copy that value from the nonvolatile memory location to this register?s ftrim bit. 7 6543210 r lolie plls cme 0 vdiv w reset: 0 0 0 0 0 0 0 1 figure 12-7. mcg pll register (mcgpll) table 12-5. mcg pll register field descriptions field description 7 lolie loss of lock interrupt enable ? determines if an interrupt request is made following a loss of lock indication. the lolie bit only has an effect when lols is set. 0 no request on loss of lock. 1 generate an interrupt request on loss of lock. 6 plls pll select ? controls whether the pll or fll is selected. if the plls bit is clear, the pll is disabled in all modes. if the plls is set, the fll is disabled in all modes. 1 pll is selected 0 fll is selected table 12-4. mcg status and control register field descriptions (continued) field description
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 187 5 cme clock monitor enable ? determines if a reset request is made following a loss of external clock indication. the cme bit must only be set to a logic 1 when either the mcg is in an operational mode that uses the external clock (fee, fbe, pee, pbe, or blpe) or the external refe rence is enabled (erclken=1 in the mcgc2 register). whenever the cme bit is set to a logic 1, the value of the range bit in the mcgc2 register must not be changed. 0 clock monitor is disabled. 1 generate a reset request on loss of external clock. 3:0 vdiv vco divider ? selects the amount to divide down the vco output of pll. the vdiv bits establish the multiplication factor (m) applied to the reference clock frequency. 0000 encoding 0 ? reserved. 0001 encoding 1 ? multiply by 4. 0010 encoding 2 ? multiply by 8. 0011 encoding 3 ? multiply by 12. 0100 encoding 4 ? multiply by 16. 0101 encoding 5 ? multiply by 20. 0110 encoding 6 ? multiply by 24. 0111 encoding 7 ? multiply by 28. 1000 encoding 8 ? multiply by 32. 1001 encoding 9 ? multiply by 36. 1010 encoding 10 ? multiply by 40. 1011 encoding 11 ? reserved (default to m=40). 11xx encoding 12-15 ? reserved (default to m=40). table 12-5. mcg pll register field descriptions (continued) field description
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 188 freescale semiconductor 12.4 functional description 12.4.1 operational modes figure 12-8. clock switching modes the nine states of the mcg are show n as a state diagram and are describe d below. the arrows indicate the allowed movements between the states. 12.4.1.1 fll engaged internal (fei) fll engaged internal (fei) is the default mode of operation and is entered when all the following conditions occur: ? clks bits are written to 00 ? irefs bit is written to 1 ? plls bit is written to 0 ? rdiv bits are written to 000. because the internal reference clock frequenc y must already be in the range of 31.25 khz to 39.0625 khz after it is trimmed, no further frequency divide is necessary. entered from any state when mcu enters stop returns to state that was active before mcu entered stop, unless reset occurs while in stop. stop pll bypassed external (pbe) pll engaged external (pee) fll engaged external (fee) fll engaged internal (fei) fll bypassed external (fbe) fll bypassed internal (fbi) irefs=1 clks=00 plls=0 irefs=0 clks=00 plls=0 irefs=1 clks=01 plls=0 irefs=0 clks=10 plls=0 irefs=0 clks=00 plls=1 irefs=0 clks=10 plls=1 irefs=0 clks=10 bdm disabled and lp=1 irefs=1 clks=01 bdm disabled and lp=1 bypassed low power internal (blpi) bypassed low power external (blpe) bdm enabled or lp=0 bdm enabled or lp=0 bdm enabled or lp=0
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 189 in fll engaged internal mode, the mcgout clock is derived from the fll clock, which is controlled by the internal reference clock. the fll clock freque ncy locks to 1024 times the reference frequency, as selected by the rdiv bits. the mcglclk is derived from the fll and the pll is disabled in a low power state. 12.4.1.2 fll engaged external (fee) the fll engaged external (fee) mode is ente red when all the following conditions occur: ? clks bits are written to 00 ? irefs bit is written to 0 ? plls bit is written to 0 ? rdiv bits are written to divide reference clock to be within the range of 31.25 khz to 39.0625 khz in fll engaged external m ode, the mcgout clock is derived from the fll cloc k which is controlled by the external reference clock. the external refere nce clock which is enabled can be an external crystal/resonator or it can be another external clock source.the fll clock frequency locks to 1024 times the reference frequency, as selected by the rdiv bi ts. the mcglclk is derive d from the fll and the pll is disabled in a low power state. 12.4.1.3 fll bypassed internal (fbi) in fll bypassed internal (fbi) mode, the mcgout clock is derived from the internal reference clock and the fll is operational but its output clock is not use d. this mode is useful to allow the fll to acquire its target frequency while the mcgout clock is driven from the internal reference clock. the fll bypassed internal mode is entere d when all the following conditions occur: ? clks bits are written to 01 ? irefs bit is written to 1 ? plls bit is written to 0 ? rdiv bits are written to 000. since the internal re ference clock frequency must already be in the range of 31.25 khz to 39.0625 khz after it is trimme d, no further frequency divide is necessary. ? lp bit is written to 0 in fll bypassed internal mode, the mcgout clock is derived from the internal reference clock. the fll clock is controlled by the internal reference clock, and the fll clock frequenc y locks to 1024 times the reference frequency, as selected by the rdiv bits. the mcglclk is derived from the fll and the pll is disabled in a low power state. 12.4.1.4 fll bypassed external (fbe) in fll bypassed external (fbe) mode , the mcgout clock is derived fr om the external reference clock and the fll is operational but its output clock is not use d. this mode is useful to allow the fll to acquire its target frequency while the mcgout clock is driven from the external reference clock. the fll bypassed external mode is entered when all the following conditions occur:
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 190 freescale semiconductor ? clks bits are written to 10 ? irefs bit is written to 0 ? plls bit is written to 0 ? rdiv bits are written to divide reference clock to be within the range of 31.25 khz to 39.0625 khz ? lp bit is written to 0 in fll bypassed external mode, the mcgout clock is derived from th e external reference clock. the external reference clock whic h is enabled can be an external crystal/ resonator or it can be another external clock source.the fll clock is cont rolled by the external reference clock, and the fll clock frequency locks to 1024 times the refere nce frequency, as select ed by the rdiv bits. the mcglclk is derived from the fll and the pll is disa bled in a low power state. note it is possible to briefly operate in fbe mode with an fll reference clock frequency that is greater than the speci fied maximum freque ncy. this can be necessary in applications that operate in pee mode using an external crystal with a frequency above 5 mhz. please see 12.5.2.4, ?example # 4: moving from fei to pee mode: external crys tal = 8 mhz, bus frequency = 8 mhz for a detailed example. 12.4.1.5 pll engaged external (pee) the pll engaged external (pee) mode is ente red when all the following conditions occur: ? clks bits are written to 00 ? irefs bit is written to 0 ? plls bit is written to 1 ? rdiv bits are written to divide reference clock to be within the range of 1 mhz to 2 mhz in pll engaged external m ode, the mcgout clock is derived from the pll cloc k which is controlled by the external reference clock. the external refere nce clock which is enabled can be an external crystal/resonator or it can be another external clock source the pll clock frequency locks to a multiplication factor, as selected by the vdiv bits, times th e reference frequency, as selected by the rdiv bits. if bdm is enabled then the mcglclk is de rived from the dco (open- loop mode) divided by two. if bdm is not enabled then the fll is disabled in a low power state.
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 191 12.4.1.6 pll bypassed external (pbe) in pll bypassed external (pbe) mode , the mcgout clock is derived fr om the external reference clock and the pll is operational but its output clock is not use d. this mode is useful to allow the pll to acquire its target frequency while the mcgout clock is driven from the external reference clock. the pll bypassed external mode is entered when all the following conditions occur: ? clks bits are written to 10 ? irefs bit is written to 0 ? plls bit is written to 1 ? rdiv bits are written to divide reference clock to be within the range of 1 mhz to 2 mhz ? lp bit is written to 0 in pll bypassed external mode, the mcgout clock is derived from th e external reference clock. the external reference clock whic h is enabled can be an external crystal/ resonator or it can be another external clock source. the pll clock frequency locks to a multiplication factor, as selected by the vdiv bits, times the reference frequency, as select ed by the rdiv bits. if bdm is enabled then the mcglclk is derived from the dco (open-loop m ode) divided by two. if bdm is not enable d then the fll is disabled in a low power state. 12.4.1.7 bypassed low power internal (blpi) the bypassed low power internal (blpi) mode is entered when all the following conditions occur: ? clks bits are written to 01 ? irefs bit is written to 1 ? plls bit is written to 0 or 1 ? lp bit is written to 1 ? bdm mode is not active in bypassed low power internal mode, the mcgout cl ock is derived from the internal reference clock. the pll and the fll are disabled at all times in bl pi mode and the mcglclk wi ll not be available for bdc communications if the bdm becomes active the mode will switch to one of the bypassed internal modes as determined by the state of the plls bit. 12.4.1.8 bypassed low power external (blpe) the bypassed low power external (b lpe) mode is entered when all the following conditions occur: ? clks bits are written to 10 ? irefs bit is written to 0 ? plls bit is written to 0 or 1 ? lp bit is written to 1 ? bdm mode is not active
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 192 freescale semiconductor in bypassed low power external mode, the mcgout cl ock is derived from the external reference clock. the external reference clock which is enabled can be an external crysta l/resonator or it can be another external clock source. the pll and the fll are disabled at all times in blpe mode and the mcglclk will not be available for bdc communications. if the bdm becomes active the mode will switch to one of the bypassed external modes as determined by the state of the plls bit. 12.4.1.9 stop stop mode is entered when ever the mcu enters a stop state. in this mode, the fll and pll are disabled and all mcg clock signals are static except in the following cases: mcgirclk will be ac tive in stop mode when all the following conditions occur: ? irclken = 1 ? irefsten = 1 mcgerclk will be active in stop mode when all the following conditions occur: ? erclken = 1 ? erefsten = 1 12.4.2 mode switching when switching between engaged inte rnal and engaged external modes the irefs bit can be changed at anytime, but the rdiv bits must be changed simultaneously so that th e reference frequency stays in the range required by the state of the plls bit (31.25 khz to 39.0625 khz if the fll is se lected, or 1 mhz to 2 mhz if the pll is select ed). after a change in the irefs value the fll or pll will begin locking again after the switch is completed. the completion of the switch is s hown by the irefst bit. for the special case of entering stop mode immediately after switching to fbe mode , if the external clock and the internal clock are disabled in stop mode, (ere fsten = 0 and irefsten = 0), it is necessary to allow 100us after the irefst bit is cleared to allow th e internal reference to s hutdown. for most cases the delay due to instruction execut ion times will be sufficient. the clks bits can also be changed at anytime, but in order for the mc glclk to be configured correctly the rdiv bits must be changed simu ltaneously so that the reference frequency stays in the range required by the state of the plls bit (31.25 khz to 39.0625 khz if the fll is sel ected, or 1 mhz to 2mhz if the pll is selected). the actual switch to the newly se lected clock will be show n by the clkst bits. if the newly selected clock is not available, th e previous clock will remain selected. for details see figure 12-8 . 12.4.3 bus frequency divider the bdiv bits can be changed at anytime and th e actual switch to the new frequency will occur immediately.
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 193 12.4.4 low power bit usage the low power bit (lp) is provided to allow the fll or pll to be disa bled and thus conserve power when these systems are not being used. howe ver, in some applicati ons it may be desirable to enable the fll or pll and allow it to lock for maximum accuracy before switching to an engaged mode. do this by writing the lp bit to 0. 12.4.5 internal reference clock when irclken is set the internal reference clock signal will be pres ented as mcgirclk, which can be used as an additional cl ock source. the mcgirclk fr equency can be re-targete d by trimming the period of the internal reference clock. this can be done by writing a new value to the trim bits in the mcgtrm register. writing a larger value will decrease the mcgirclk frequency, and writing a smaller value to the mcgtrm register will increa se the mcgirclk frequency. the trim bits will effect the mcgout frequency if the mcg is in fll engaged internal (fei), fll bypassed internal (fbi), or bypassed low power internal (blpi) mode. the trim and ftrim va lue is initialized by por but is not affected by other resets. until mcgirclk is trimmed, programming low refere nce divider (rdiv) factors may result in mcgout frequencies that exceed the maximum chip-l evel frequency and violate the chip-level clock timing specifications (see the device overview chapter). if irefsten and irclken bits are both set, the internal reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. 12.4.6 external reference clock the mcg module can support an extern al reference clock with freque ncies between 31 .25 khz to 5 mhz in fee and fbe modes, 1 mhz to 16 mhz in pee and pbe modes, and 0 to 40 mhz in blpe mode. when erclken is set, the external reference clock signal will be presented as mcgerclk, which can be used as an additional clock sour ce. when irefs = 1, the external re ference clock will not be used by the fll or pll and will only be us ed as mcgerclk. in these modes, the frequency can be equal to the maximum frequency the chip-level timi ng specifications will support (see the device overview chapter). if erefsten and erclken bits are both set or th e mcg is in fee, fbe, pee, pbe or blpe mode, the external reference clock will keep running during stop mode in orde r to provide a fast recovery upon exiting stop. if cme bit is written to 1, the clock monitor is enab led. if the external reference falls below a certain frequency (f loc_high or f loc_low depending on the range bit in the mcgc2), the mcu will reset. the loc bit in the system reset status (srs) register will be set to indicate the error. 12.4.7 fixed frequency clock the mcg presents the divided refere nce clock as mcgffclk for use as an additional clock source. the mcgffclk frequency must be no more than 1/4 of the mcgout frequency to be valid. because of this requirement, the mcgffclk is not valid in bypass modes for the following combinations of bdiv and rdiv values:
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 194 freescale semiconductor ? bdiv=00 (divide by 1), rdiv < 010 bdiv=01 (divide by 2), rdiv < 011 12.5 initialization / application information this section describes how to initialize and configure the mcg module in application. the following sections include examples on how to initialize the mc g and properly switch betw een the various available modes. 12.5.1 mcg module initialization sequence the mcg comes out of reset configured for fei mode with the bdiv set for divide-by-2. the internal reference will stabilize in t irefst microseconds before the fll can acquire lock. as soon as the internal reference is stable, the f ll will acquire lock in t fll_lock milliseconds. upon por, the internal reference will require trimming to guarantee an accurate clock. freescale recommends using flash location 0xf fae for storing the fine trim bit, ftrim in the mcgsc register, and 0xffaf for storing the 8-bit trim value in the mcgtrm register. the mcu will not automatically copy the values in these flash locati ons to the respective registers. therefore, user code must copy these values from flash to the registers. note the bdiv value must not be changed to divide-by-1 with out first trimming the internal reference. fa ilure to do so could resu lt in the mcu running out of specification. 12.5.1.1 initializing the mcg because the mcg comes out of reset in fei mode, th e only mcg modes which can be directly switched to upon reset are fee, fb e, and fbi modes (see figure 12-8 ). reaching any of th e other modes requires first configuring the mcg for one of these three initial modes. care mu st be taken to check relevant status bits in the mcgsc register reflecting a ll configuration changes within each mode. to change from fei mode to fee or fbe modes, follow this procedure: 1. enable the external clock source by se tting the appropriate bits in mcgc2. 2. write to mcgc1 to se lect the clock mode. ? if entering fee, set rdiv appropriately, clear the irefs bit to switch to the external reference, and leave the clks bits at %00 so that the output of the fll is selected as the system clock source. ? if entering fbe, clear the irefs bit to switch to the external reference and change the clks bits to %10 so that the external reference clock is selected as the system clock source. the rdiv bits must also be set appropriately here according to the external reference frequency because although the fll is bypassed, it is still on in fbe mode. ? the internal reference can optionally be kept running by setting the irclken bit. this is useful if the applicati on will switch back and forth between internal and external modes. for
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 195 minimum power consumption, leave the internal reference disabled while in an external clock mode. 3. after the proper configuration bits have been set, wait for the affe cted bits in the mcgsc register to be changed appropriately, reflecting that the mcg has moved into the proper mode. ? if erclken was set in step 1 or the mcg is in fee, fbe, pee, pbe, or blpe mode, and erefs was also set in step 1, wait here for th e oscinit bit to become set indicating that the external clock source has finished its initializa tion cycles and stabilize d. typical crystal startup times are given in appendix a, ?electrical characteristics?. ? if in fee mode, check to make sure the irefst bit is cleared and the lock bit is set before moving on. ? if in fbe mode, check to make sure the irefst bit is cleared, the lock bit is set, and the clkst bits have changed to %10 indicating the external reference clock has been appropriately selected. although the fll is bypassed in fbe mode, it is st ill on and will lock in fbe mode. to change from fei clock mode to fb i clock mode, follow this procedure: 1. change the clks bits to %01 so that the internal reference clock is selected as the system clock source. 2. wait for the clkst bits in the mcgsc register to change to %01, indicating that the internal reference clock has been appropriately selected. 12.5.2 mcg mode switching when switching between operational modes of the mcg, cert ain configuration bits must be changed in order to properly move from one mode to another. each time any of these bits are changed (plls, irefs, clks, or erefs), the corresponding bits in the mcgsc register (pllst, irefst, clkst, or oscinit) must be checked before m oving on in the application software. additionally, care must be taken to ensure that the re ference clock divider (rdiv) is set properly for the mode being switched to. for instance, in pee mode, if using a 4 mhz cr ystal, rdiv must be set to %001 (divide-by-2) or %010 (divide-by-4) in order to divide the external reference down to the required frequency between 1 and 2 mhz. the rdiv and irefs bits must alwa ys be set properly before changing the plls bit so that the fll or pll clock has an appropriate refere nce clock frequency to switch to.
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 196 freescale semiconductor the table below shows mcgout frequency calculations using rdiv, bdiv, and vdiv settings for each clock mode. the bus frequency is equal to mcgout divided by 2. 1 r is the reference divider selected by the rdiv bits, b is the bus frequency divider selected by the bdiv bits, and m is the multiplier selected by the vdiv bits. this section will include 3 mode sw itching examples using a 4 mhz extern al crystal. if using an external clock source less than 1 mhz, the mcg must not be configured for any of the pll modes (pee and pbe). 12.5.2.1 example # 1: moving from fei to pee mode: external crystal = 4 mhz, bus frequency = 8 mhz in this example, the mcg will move through the proper operational modes from fei to pee mode until the 4 mhz crystal reference frequency is set to achieve a bus frequency of 8 mhz. because the mcg is in fei mode out of reset, this example also shows how to initialize the mcg for pee mode out of reset. first, the code sequence will be describe d. then a flowchart will be included which illustrates the sequence. 1. first, fei must transition to fbe mode: a) mcgc2 = 0x36 (%00110110) ? bdiv (bits 7 and 6) set to %00, or divide-by-1 ? range (bit 5) set to 1 because the frequency of 4 mhz is within the high frequency range ? hgo (bit 4) set to 1 to configure ex ternal oscillator for high gain operation ? erefs (bit 2) set to 1, because a crystal is being used ? erclken (bit 1) set to 1 to ensure the external reference clock is active b) loop until oscinit (bit 1) in mcgsc is 1, i ndicating the crystal selected by the erefs bit has been initialized. c) mcgc1 = 0xb8 (%10111000) table 12-6. mcgout frequency calculation options clock mode f mcgout 1 note fei (fll engaged internal) (f int * 1024) / b typical f mcgout = 16 mhz immediately after reset. rdiv bits set to %000. fee (fll engaged external) (f ext / r *1024) / b f ext / r must be in the range of 31.25 khz to 39.0625 khz fbe (fll bypassed external) f ext / b f ext / r must be in the range of 31.25 khz to 39.0625 khz fbi (fll bypassed internal) f int / b typical f int = 32 khz pee (pll engaged external) [(f ext / r) * m] / b f ext / r must be in the range of 1 mhz to 2 mhz pbe (pll bypassed external) f ext / b f ext / r must be in the range of 1 mhz to 2 mhz blpi (bypassed low power internal) f int / b blpe (bypassed low power external) f ext / b
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 197 ? clks (bits 7 and 6) set to %10 in order to se lect external reference clock as system clock source ? rdiv (bits 5-3) set to %11 1, or divide-by-128 because 4 mhz / 128 = 31.25 khz which is in the 31.25 khz to 39.0625 khz range required by the fll ? irefs (bit 2) cleared to 0, selecting the external reference clock d) loop until irefst (bit 4) in mcgsc is 0, i ndicating the external reference is the current source for the reference clock e) loop until clkst (bits 3 and 2) in mcgsc ar e %10, indicating that th e external reference clock is selected to feed mcgout 2. then, fbe must transition either directly to pb e mode or first through blpe mode and then to pbe mode: a) blpe: if a transition through blpe mode is de sired, first set lp (bit 3) in mcgc2 to 1. b) blpe/pbe: mcgc1 = 0x90 (%10010000) ? rdiv (bits 5-3) set to %010, or divide-by-4 because 4 mhz / 4 = 1 mhz which is in the 1 mhz to 2 mhz range required by the pll. in blpe mode, the configuration of the rdiv does not matter because both th e fll and pll are disabled. ch anging them only sets up the the dividers for pll usage in pbe mode c) blpe/pbe: mcgc3 = 0x44 (%01000100) ? plls (bit 6) set to 1, selects the pll. in bl pe mode, changing this bit only prepares the mcg for pll usage in pbe mode ? vdiv (bits 3-0) set to %0100, or mu ltiply-by-16 because 1 mhz reference 16 = 16 mhz. in blpe mode, the configuration of the vdiv bits does not matter because the pll is disabled. changing them only sets up the multiply value for pll usage in pbe mode d) blpe: if transitioning through blpe mode, clear lp (bit 3) in mcgc2 to 0 here to switch to pbe mode e) pbe: loop until pllst (bit 5) in mcgsc is se t, indicating that the current source for the plls clock is the pll f) pbe: then loop until lock (bit 6) in mcgsc is set, indicating that the pll has acquired lock 3. last, pbe mode transitions into pee mode: a) mcgc1 = 0x10 (%00010000) ? clks (bits7 and 6) in mcgsc1 set to %00 in order to select the out put of the pll as the system clock source ? loop until clkst (bits 3 and 2) in mcgsc are %11, indicating that the pll output is selected to feed mcgout in the current clock mode b) now, with an rdiv of divide-by-4, a bdiv of divide-by-1, and a vdiv of multiply-by-16, mcgout = [(4 mhz / 4) 16] / 1 = 16 mhz, and the bus frequency is mcgout / 2, or 8 mhz
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 198 freescale semiconductor figure 12-9. flowchart of fei to pee m ode transition usin g a 4 mhz crystal mcgc2 = $36 check oscinit = 1 ? mcgc1 = $b8 check irefst = 0? check clkst = %10? enter blpe mode ? mcgc2 = $3e (lp = 1) mcgc1 = $90 mcgc3 = $44 in blpe mode ? (lp=1) mcgc2 = $36 (lp = 0) check pllst = 1? mcgc1 = $10 check lock = 1? check clkst = %11? continue in pee mode start i n fei mode yes yes yes yes yes yes yes yes no no no no no no no no
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 199 12.5.2.2 example # 2: moving from pee to blpi mode: external crystal = 4 mhz, bus frequency =16 khz in this example, the mc g will move through the proper operationa l modes from pee mode with a 4 mhz crystal configured for an 8 mhz bus frequency (see pr evious example) to blpi mode with a 16 khz bus frequency.first, the code sequence wi ll be described. then a flowchart will be included which illustrates the sequence. 1. first, pee must tr ansition to pbe mode: a) mcgc1 = 0x90 (%10010000) ? clks (bits 7 and 6) set to %10 in order to sw itch the system clock source to the external reference clock b) loop until clkst (bits 3 and 2) in mcgsc ar e %10, indicating that th e external reference clock is selected to feed mcgout 2. then, pbe must transition either directly to fb e mode or first through blpe mode and then to fbe mode: a) blpe: if a transition through blpe mode is de sired, first set lp (bit 3) in mcgc2 to 1 b) blpe/fbe: mcgc1 = 0xb8 (%10111000) ? rdiv (bits 5-3) set to %11 1, or divide-by-128 because 4 mhz / 128 = 31.25 khz which is in the 31.25 khz to 39.0625 khz range required by the fll. in blpe mode, the configuration of the rdiv does not matter because both the fll and pll are disabled. changing them only sets up the dividers for fll usage in fbe mode c) blpe/fbe: mcgc3 = 0x04 (%00000100) ? plls (bit 6) clear to 0 to select the fll. in blpe mode, changing this bit only prepares the mcg for fll usage in fbe mode. with p lls = 0, the vdiv value does not matter. d) blpe: if transitioning through blpe mode, clear lp (bit 3) in mcgc2 to 0 here to switch to fbe mode e) fbe: loop until pllst (bit 5) in mcgsc is cl ear, indicating that the current source for the plls clock is the fll f) fbe: optionally, loop until lock (bit 6) in the mcgsc is set, indicating that the fll has acquired lock. although the fll is bypassed in fbe mode, it is still enabled and running. 3. next, fbe mode transitions into fbi mode: a) mcgc1 = 0x44 (%01000100) ? clks (bits7 and 6) in mcgsc1 set to %01 in order to switch the system clock to the internal reference clock ? irefs (bit 2) set to 1 to select the internal reference clock as the reference clock source ? rdiv (bits 5-3) set to %000, or divide-by-1 because the trimme d internal reference must be within the 31.25 khz to 39.0625 khz range required by the fll b) loop until irefst (bit 4) in mcgsc is 1, indicating the internal reference clock has been selected as the reference clock source c) loop until clkst (bits 3 and 2) in mcgsc ar e %01, indicating that the internal reference clock is selected to feed mcgout
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 200 freescale semiconductor 4. lastly, fbi transitions into fbilp mode. a) mcgc2 = 0x08 (%00001000) ? lp (bit 3) in mcgsc is 1 figure 12-10. flowchart of pee to blpi mode transition using a 4 mhz crystal mcgc1 = $90 check clkst = %10 ? mcgc2 = $3e mcgc1 = $44 check irefst = 0? check clkst = %01? continue in blpi mode start in pee mode mcgc1 = $b8 mcgc3 = $04 enter blpe mode ? in blpe mode ? (lp=1) mcgc2 = $36 (lp = 0) check pllst = 0? optional: = 1? mcgc2 = $08 yes yes yes yes yes yes yes no no no no no no no check lock
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 201 12.5.2.3 example #3: moving from blpi to fee mode: external crystal = 4 mhz, bus frequency = 16 mhz in this example, the mcg will m ove through the proper operational m odes from blpi mode at a 16 khz bus frequency running off of the internal reference clock (see previous example) to fee mode using a 4 mhz crystal configured for a 16 mhz bus frequency. fi rst, the code sequence will be described. then a flowchart will be included wh ich illustrates the sequence. 1. first, blpi must tr ansition to fbi mode. a) mcgc2 = 0x00 (%00000000) ? lp (bit 3) in mcgsc is 0 b) optionally, loop until lock (bit 6) in the mc gsc is set, indicating th at the fll has acquired lock. although the fll is bypassed in fbi mode, it is still enabled and running. 2. next, fbi will transition to fee mode. a) mcgc2 = 0x36 (%00110110) ? range (bit 5) set to 1 because the frequency of 4 mhz is within the high frequency range ? hgo (bit 4) set to 1 to configure ex ternal oscillator for high gain operation ? erefs (bit 2) set to 1, because a crystal is being used ? erclken (bit 1) set to 1 to ensure the external reference clock is active b) loop until oscinit (bit 1) in mcgsc is 1, i ndicating the crystal selected by the erefs bit has been initialized. c) mcgc1 = 0x38 (%00111000) ? clks (bits 7 and 6) set to %00 in order to select the output of the fll as system clock source ? rdiv (bits 5-3) set to %11 1, or divide-by-128 because 4 mhz / 128 = 31.25 khz which is in the 31.25 khz to 39.0625 khz range required by the fll ? irefs (bit 1) cleared to 0, selecting the external reference clock d) loop until irefst (bit 4) in mcgsc is 0, indicating the external reference clock is the current source for the reference clock e) optionally, loop until lock (bit 6) in th e mcgsc is set, indicating that the fll has reacquired lock. f) loop until clkst (bits 3 and 2) in mcgsc are %00, indicating that the output of the fll is selected to feed mcgout
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 202 freescale semiconductor figure 12-11. flowchart of blpi to fee mode transition using a 4 mhz crystal 12.5.2.4 example # 4: moving from fei to pee mode: external crystal = 8 mhz, bus frequency = 8 mhz in this example, the mcg will move through the proper operational modes from fei to pee mode until the 8 mhz crystal reference frequency is set to achieve a bus frequency of 8 mhz. this example is similar to example number one except that in this case the frequenc y of the external crystal is 8 mhz instead of 4 mhz. special consideration must be taken with this case since there is a period of time along the way from fei mode to pee mode where the fll operate s based on a reference clock with a frequency that is greater than the maximum allowed for the fll. this occurs because with an 8 mhz mcgc2 = $36 check oscinit = 1 ? mcgc1 = $38 check irefst = 0? check clkst = %00? continue in fee mode start i n blpi mode yes yes no no no mcgc2 = $00 optional: check lock = 1? yes no yes optional: check lock = 1? yes no
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 203 external crystal and a maximum refe rence divider factor of 128, the resu lting frequency of the reference clock for the fll is 62.5 khz (greater than the 39.0625 khz maximum allowed). care must be taken in the software to minimize the amount of time spent in this state where the fll is operating in this condition. the following code sequence describe s how to move from fei mode to pee mode until the 8 mhz crystal reference frequency is set to achiev e a bus frequency of 8 mhz. because the mcg is in fei mode out of reset, this example also shows how to initialize th e mcg for pee mode out of reset. first, the code sequence will be described. then a flowchart will be included which illustrates the sequence. 1. first, fei must transition to fbe mode: a) mcgc2 = 0x36 (%00110110) ? bdiv (bits 7 and 6) set to %00, or divide-by-1 ? range (bit 5) set to 1 because the frequency of 8 mhz is within the high frequency range ? hgo (bit 4) set to 1 to configure ex ternal oscillator for high gain operation ? erefs (bit 2) set to 1, because a crystal is being used ? erclken (bit 1) set to 1 to ensure the external reference clock is active b) loop until oscinit (bit 1) in mcgsc is 1, i ndicating the crystal selected by the erefs bit has been initialized. c) block interrupts (if applicable by se tting the interrupt bit in the ccr). d) mcgc1 = 0xb8 (%10111000) ? clks (bits 7 and 6) set to %10 in order to se lect external reference clock as system clock source ? rdiv (bits 5-3) set to %111, or divide-by-128. note 8 mhz / 128 = 62.5 khz wh ich is greater than the 31.25 khz to 39.0625 khz range required by the fll. therefor e after the transition to fbe is complete, software must progress th rough to blpe mode immediately by setting the lp bit in mcgc2. ? irefs (bit 2) cleared to 0, selecting the external reference clock e) loop until irefst (bit 4) in mcgsc is 0, indicating the external reference is the current source for the reference clock f) loop until clkst (bits 3 and 2) in mcgsc ar e %10, indicating that th e external reference clock is selected to feed mcgout 2. then, fbe mode transi tions into blpe mode: a) mcgc2 = 0x3e (%00111110) ? lp (bit 3) in mcgc2 to 1 (blpe mode entered) note there must be no extra st eps (including interrupts) between steps 1d and 2a. b) enable interrupts (if applicable by clearing the interrupt bit in the ccr).
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 204 freescale semiconductor c) mcgc1 = 0x98 (%10011000) ? rdiv (bits 5-3) set to %011, or divide-by-8 because 8 mhz / 8= 1 mhz which is in the 1 mhz to 2 mhz range required by the pll. in blpe mode, the configuration of the rdiv does not matter because both th e fll and pll are disabled. ch anging them only sets up the the dividers for pll usage in pbe mode d) mcgc3 = 0x44 (%01000100) ? plls (bit 6) set to 1, selects the pll. in bl pe mode, changing this bit only prepares the mcg for pll usage in pbe mode ? vdiv (bits 3-0) set to %0100, or multiply-by-16 because 1 mhz reference * 16 = 16 mhz. in blpe mode, the configuration of the vdiv bits does not matter because the pll is disabled. changing them only sets up the multiply value for pll usage in pbe mode e) loop until pllst (bit 5) in mc gsc is set, indicatin g that the current source for the plls clock is the pll 3. then, blpe mode transitions into pbe mode: a) clear lp (bit 3) in mcgc2 to 0 here to switch to pbe mode b) then loop until lock (bit 6) in mcgsc is set, indicating that the pll has acquired lock 4. last, pbe mode transitions into pee mode: a) mcgc1 = 0x18 (%00011000) ? clks (bits7 and 6) in mcgsc1 set to %00 in order to select the out put of the pll as the system clock source ? loop until clkst (bits 3 and 2) in mcgsc are %11, indicating that the pll output is selected to feed mcgout in the current clock mode b) now, with an rdiv of divide-by-8, a bdiv of divide-by-1, and a vdiv of multiply-by-16, mcgout = [(8 mhz / 8) 16] / 1 = 16 mhz, and the bus frequency is mcgout / 2, or 8 mhz
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 205 figure 12-12. flowchart of fei to pee m ode transition using a 8 mhz crystal mcgc2 = $36 check oscinit = 1 ? mcgc1 = $b8 check irefst = 0? check clkst = %10? mcgc2 = $3e (lp = 1) mcgc1 = $98 mcgc3 = $44 mcgc2 = $36 (lp = 0) check pllst = 1? mcgc1 = $18 check lock = 1? check clkst = %11? continue in pee mode start i n fei mode yes yes yes yes yes yes no no no no no no
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 206 freescale semiconductor 12.5.3 calibrating the intern al reference clock (irc) the irc is calibrated by writing to the mcgtrm regist er first, then using the ftrim bit to ?fine tune? the frequency. we will refer to th is total 9-bit value as the trim value, ranging fr om 0x000 to 0x1ff, where the ftrim bit is the lsb. the trim value after a por is always 0x100 (mcgtr m = 0x80 and ftrim = 0). writing a larger value will decrease the frequency and smalle r values will increase the frequency. the trim value is linear with the period, except that slight variat ions in wafer fab pro cessing produce slight non-li nearities between trim value and period. these non-li nearities are why an iterat ive trimming approach to se arch for the best trim value is recommended. in example #4 later in this section, this approach will be demonstrated. after a trim value has been found for a device, this va lue can be stored in fl ash memory to save the value. if power is removed from the device, the irc can easily be re-trimmed by copyi ng the saved value from flash to the mcg registers. freescale identi fies recommended flash lo cations for storing the trim value for each mcu. consult th e memory map in the data sheet for these locations. on devices that are factory trimmed, the factory trim value will be stored in these locations. 12.5.3.1 example #5: internal reference clock trim for applications that require a tight frequency tolerance, a trimming proc edure is provided that will allow a very accurate internal clock source . this section outlines one example of trimming the internal oscillator. many other possible trimming procedur es are valid and can be used. in the example below, the mcg trim will be cali brated for the 9-bit mcgtrm and ftrim collective value. this value will be referred to as trmval.
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 207 figure 12-13. trim procedure in this particular case, the mcu ha s been attached to a pcb and the entire assembly is undergoing final test with automated test equipment. a separate si gnal or message is provided to the mcu operating under user provided software contro l. the mcu initiates a trim procedure as outlined in figure 12-13 while the tester supplies a precision reference signal. if the intended bus frequency is near the maximum allowed fo r the device, it is re commended to trim using a reference divider value (rdi v setting) of twice the final value. af ter the trim procedur e is complete, the reference divider can be restored. this will prevent accid ental overshoot of the maximum clock frequency. initial conditions: 1) clock supplied from ate has 500 s duty period 2) mcg configured for internal reference with 8mhz bus start trim procedure continue case statement count > expected = 500 . measure incoming clock width trmval = $100 count < expected = 500 count = expected = 500 trmval = trmval = trmval - 256/ (2**n) trmval + 256/ (2**n) n = n + 1 (count = # of bus clocks / 8) (decreasing trmval increases the frequency) (increasing trmval decreases the frequency) no yes is n > 9? (running too slow) (running too fast) n=1 store mcgtrm and ftrim values in non-volatile memory
multi-purpose clock generator (s08mcgv1) MC9S08JM16 series data sheet, rev. 2 208 freescale semiconductor
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 209 chapter 13 real-time counter (s08rtcv1) 13.1 introduction the real-time counter (rtc) consists of one 8-bit counter, one 8-bi t comparator, several binary-based and decimal-based prescaler dividers, two clock sources, and one progr ammable periodic interrupt. this module can be used for time-of-day, calendar or any task scheduling functi ons. it can also se rve as a cyclic wakeup from low power modes without the need for external components.
chapter 13 real-time counter (s08rtcv1) MC9S08JM16 series data sheet, rev. 2 210 freescale semiconductor figure 13-1. MC9S08JM16 series bl ock diagram highlighting rtc block ptc1/sda ptc0/scl v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta5, pta0 pte0/txd1 pte1/rxd1 ptd1/adp9/acmp? ptd0/adp8/acmp+ ptc5/rxd2 ptc4 ptc3/txd2 ptc2 port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi1) user flash (in bytes) user ram (in bytes) on-chip ice and debug module (dbg) hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pu llup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. pin contains integrated pullup device. 5. when pin functions as kbi (kbipen = 1) and associated pin is configured to enable the pullup device, kbedgn can be used to reco nfigure the pullup as a pulldown device. 2-channel timer/pwm module (tpm2) ptb5/kbip5/adp5 port b pte5/mosi1 pte4/miso1 pte6/spsck1 pte7/ss1 hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset v ssad v ddad v refh analog-to-digital converter (adc) 4-channel timer/pwm module (tpm1) ptd7 2 ptb4/kbip4/adp4 ptg3/kbip7 ptg2/kbip6 port g 8-channel, 12-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg4/xtal ptg5/extal irq/tpmclk rxd2 txd2 sda scl 6 kbipx kbipx tpmclk spsck1 ss1 miso1 mosi1 tpmclk tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 2 4 usb sie usb endpoint ram full speed usb transceiver usbdp usbdn miso2 ss2 spsck2 mosi2 ptb1/mosi2/adp1 ptb0/miso2/adp0 8-/16-bit real-time counter (rtc) ptb3/ss2 /adp3 ptb2/spsck2/adp2 tpm1chx 3 tpm2ch1 tpm2ch0 2 analog comparator (acmp) system usb 3.3 v voltage regulator v usb33 1024 acmpo acmp+ acmp? ptd2/kbip2/acmpo 8-/16-bit serial peripheral interface module (spi2) mc9s08jm8 = 8,192 MC9S08JM16 = 16,384 v ssosc
real-time counter (s08rtcv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 211 13.1.1 features features of the rtc module include: ? 8-bit up-counter ? 8-bit modulo match limit ? software controllable periodic interrupt on match ? three software selectable clock sources for input to prescaler with select able binary-based and decimal-based divider values ? 1 khz internal low-power oscillator (lpo) ? external clock (erclk) ? 32 khz internal clock (irclk) 13.1.2 modes of operation this section defines the operation in stop, wait and background debug modes. 13.1.2.1 wait mode the rtc continues to run in wait mode if enabled before executing the appropriate instruction. therefore, the rtc can bring the mcu out of wait mode if the real-time interrupt is enab led. for lowest possible current consumption, the rtc must be stopped by software if not needed as an interrupt source during wait mode. 13.1.2.2 stop modes the rtc continues to run in stop2 or stop3 mode if the rtc is enabled before executing the stop instruction. therefore, the rtc can bring the mcu out of st op modes with no external components, if the real-time interrupt is enabled. the lpo clock can be used in stop2 and stop3 modes. erclk and irclk clocks are only available in stop3 mode. power consumption is lower when all clock sources are disabled, but in that case, the real-time interrupt cannot wake up the mcu from stop modes. 13.1.2.3 active background mode the rtc suspends all counting duri ng active background mode until the microcontroll er returns to normal user operating mode. counti ng resumes from the suspe nded value as long as the rtc mod register is not written and the rtcps and rt clks bits are not altered.
real-time counter (s08rtcv1) MC9S08JM16 series data sheet, rev. 2 212 freescale semiconductor 13.1.3 block diagram the block diagram for the rtc module is shown in figure 13-2 . figure 13-2. real-time coun ter (rtc) block diagram 13.2 external signal description the rtc does not include any off-chip signals. 13.3 register definition the rtc includes a status and control register, an 8- bit counter register, and an 8-bit modulo register. refer to the direct-page register summary in the memo ry section of this document for the absolute address assignments for all rtc registers.this section refers to registers and control bi ts only by their names and relative address offsets. table 13-1 is a summary of rtc registers. table 13-1. rtc register summary name 7 6 5 4 3210 rtcsc r rtif rtclks rtie rtcps w rtccnt r rtccnt w rtcmod r rtcmod w clock source select prescaler divide-by 8-bit counter (rtccnt) 8-bit modulo (rtcmod) 8-bit comparator rtif rtie background v dd rtc interrupt request d q r e lpo rtc clock mode erclk irclk rtclks write 1 to rtif rtcps rtclks[0]
real-time counter (s08rtcv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 213 13.3.1 rtc status and co ntrol register (rtcsc) rtc sc contains the real-time interrupt status flag (rtif), the clock se lect bits (rtclks), the real-time interrupt enable bit (rtie), and the prescaler select bits (rtcps). 7 6543210 r rtif rtclks rtie rtcps w reset: 0 0 0 0 0 0 0 0 figure 13-3. rtc status and control register (rtcsc) table 13-2. rtcsc field descriptions field description 7 rtif real-time interrupt flag this status bit indicates the rt c counter register reached the value in the rtc modulo register. writing a logic 0 has no effect. writing a logic 1 clears the bit and the real-time interrupt request. reset clears rtif. 0 rtc counter has not reached the value in the rtc modulo register. 1 rtc counter has reached the value in the rtc modulo register. 6 ? 5 rtclks real-time clock source select. these two read/write bits select the clock source input to the rtc prescaler. changing the clock source clears the prescaler and rt ccnt counters. when selecting a clock source, ensure that the clock source is properly enabled (if applicab le) to ensure correct operation of the rtc. reset clears rtclks. 00 real-time clock source is the 1 khz low power oscillator (lpo) 01 real-time clock source is the external clock (erclk) 1x real-time clock source is the internal clock (irclk) 4 rtie real-time interrupt enable. th is read/write bit enables real-time interrupts. if rtie is set, then an interrupt is generated when rtif is set. reset clears rtie. 0 real-time interrupt requests are disabled. use software polling. 1 real-time interrupt requests are enabled. 3?0 rtcps real-time clock prescaler select. these four read/write bits select binary-based or decimal-based divide-by values for the clock source. see table 13-3 . changing the prescaler value clears the prescaler and rtccnt counters. reset clears rtcps. table 13-3. rtc prescaler divide-by values rtclks[0] rtcps 0 1 2 3 4 5 6 7 8 9 101112 13 14 15 0 off 2 3 2 5 2 6 2 7 2 8 2 9 2 10 12 2 2 10 2 4 10 2 5x10 2 10 3 1 off 2 10 2 11 2 12 2 13 2 14 2 15 2 16 10 3 2x10 3 5x10 3 10 4 2x10 4 5x10 4 10 5 2x10 5
real-time counter (s08rtcv1) MC9S08JM16 series data sheet, rev. 2 214 freescale semiconductor 13.3.2 rtc counter register ( rtc cnt) rtc cnt is the read-only value of the cu rrent rtc count of the 8-bit counter. 13.3.3 rtc modulo register ( rtc mod) 13.4 functional description the rtc is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with binary-b ased and decimal-based selectable values. the module also contains software selectable interrupt logic. after any mcu reset, the counter is stopped and reset to 0x 00, the modulus register is set to 0x00, and the prescaler is off. the 1 khz internal oscillator clock is selected as th e default clock source. to start the prescaler, write any value other than zer o to the prescaler select bits (rtcps). three clock sources are software selectable: the low power oscillator clock (lpo), the external clock (erclk), and the internal clock (irclk). the rtc cl ock select bits (rtclks) select the desired clock source. if a different value is written to rtclks, the prescaler and rtccnt counters are reset to 0x00. 7 6543210 r rtccnt w reset: 0 0 0 0 0 0 0 0 figure 13-4. rtc counter register (rtccnt) table 13-4. rtccnt field descriptions field description 7:0 rtccnt rtc count. these eight read-only bits c ontain the current value of the 8-bit count er. writes have no effect to this register. reset, writing to rtcmod, or writing differen t values to rtclks and rtcp s clear the count to 0x00. 7 6543210 r rtcmod w reset: 0 0 0 0 0 0 0 0 figure 13-5. rtc modulo register (rtcmod) table 13-5. rtcmod field descriptions field description 7:0 rtcmod rtc modulo. these eight read/write bits contain the modulo value used to reset the count to 0x00 upon a compare match and set the rtif status bit. a value of 0x00 sets the rtif bit on each rising edge of the prescaler output. writing to rtcmod resets the prescaler and the rtccnt counters to 0x00. reset sets the modulo to 0x00.
real-time counter (s08rtcv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 215 rtcps and the rtclks[0] bit select the desired divide-by value. if a different value is written to rtcps, the prescaler and rtccnt counters are reset to 0x00. table 13-6 shows different prescaler period values. the rtc modulo register ( rtc mod) allows the compare value to be set to any value from 0x00 to 0xff. when the counter is active, the count er increments at the se lected rate until the count matches the modulo value. when these values match, the counter resets to 0x00 and continues counting. th e real-time interrupt flag (rtif) is set when a match occurs. the flag sets on the transition from the modulo value to 0x00. writing to rtc mod resets the prescaler a nd the rtccnt counters to 0x00. the rtc allows for an interrupt to be generated when rtif is set. to enable the real-time interrupt, set the real-time interrupt enable bit (rtie) in rtc sc. rtif is cleared by writing a 1 to rtif. 13.4.1 rtc operation example this section shows an example of the rtc operation as the counter reaches a matching value from the modulo register. table 13-6. prescaler period rtcps 1 khz internal clock (rtclks = 00) 1 mhz external clock (rtclks = 01) 32 khz internal clock (rtclks = 10) 32 khz internal clock (rtclks = 11) 0000 off off off off 0001 8 ms 1.024 ms 250 s3 2 m s 0010 32 ms 2.048 ms 1 ms 64 ms 0011 64 ms 4.096 ms 2 ms 128 ms 0100 128 ms 8.192 ms 4 ms 256 ms 0101 256 ms 16.4 ms 8 ms 512 ms 0110 512 ms 32.8 ms 16 ms 1.024 s 0111 1.024 s 65.5 ms 32 ms 2.048 s 1000 1 ms 1 ms 31.25 s 31.25 ms 1001 2 ms 2 ms 62.5 s6 2 . 5 m s 1010 4 ms 5 ms 125 s 156.25 ms 1011 10 ms 10 ms 312.5 s 312.5 ms 1100 16 ms 20 ms 0.5 ms 0.625 s 1101 0.1 s 50 ms 3.125 ms 1.5625 s 1110 0.5 s 0.1 s 15.625 ms 3.125 s 1111 1 s 0.2 s 31.25 ms 6.25 s
real-time counter (s08rtcv1) MC9S08JM16 series data sheet, rev. 2 216 freescale semiconductor figure 13-6. rtc counter overflow example in the example of figure 13-6 , the selected clock source is the 1 kh z internal oscillator clock source. the prescaler (rtcps) is set to 0xa or divide-by-4. the modulo value in the rtcmod register is set to 0x55. when the counter, rtccnt, reaches the modulo value of 0x55, the counter overflows to 0x00 and continues counting. the real-time interrupt flag, rt if, sets when the counter value changes from 0x55 to 0x00. a real-time interrupt is generated wh en rtif is set, if rtie is set. 13.5 initialization/application information this section provides example code to give some basic direction to a user on how to initialize and configure the rtc module. the example so ftware is implemented in c language. the example below shows how to implement time of day with the rtc using the 1 khz clock source to achieve the lowest possible power consumption. because the 1 khz clock source is not as accurate as a crystal, software can be added for any adjustments. for accuracy without adjust ments at the expense of additional power consumption, the external clock (erclk) or the internal clock (i rclk) can be selected with appropriate presca ler and modulo values. /* initialize the elapsed time counters */ seconds = 0; minutes = 0; hours = 0; days=0; /* configure rtc to interrupt every 1 second from 1-khz clock source */ rtcmod.byte = 0x00; rtcsc.byte = 0x1f; /********************************************************************** function name : rtc_isr notes : interrupt service routine for rtc module. **********************************************************************/ #pragma trap_proc void rtc_isr(void) { /* clear the interrupt flag */ 0x55 0x55 0x54 0x53 0x52 0x00 0x01 rtcmod rtif rtccnt rtc clock (rtcps = 0xa) internal 1 khz clock source
real-time counter (s08rtcv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 217 rtcsc.byte = rtcsc.byte | 0x80; /* rtc interrupts every 1 second */ seconds++; /* 60 seconds in a minute */ if (seconds > 59){ minutes++; seconds = 0; } /* 60 minutes in an hour */ if (minutes > 59){ hours++; minutes = 0; } /* 24 hours in a day */ if (hours > 23){ days ++; hours = 0; }
real-time counter (s08rtcv1) MC9S08JM16 series data sheet, rev. 2 218 freescale semiconductor
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 219 chapter 14 serial communications interface (s08sciv4) 14.1 introduction the MC9S08JM16 series include two independent serial communications interface (sci) modules, which are sometimes called universal asynchronous receiver/t ransmitters (uarts). typi cally, these systems are used to connect to the rs232 serial input/output (i/o) port of a personal computer or workstation, but they can also be used to communicate with other embedded controllers. a flexible, 13-bit, modulo-based baud rate generator supports a broad range of standard baud rates beyond 115.2 kbaud. transmit and receive within the same sci use a common baud rate, and each sci module has a separate baud rate generator. this sci system offers many adva nced features not commonly found on other asynchronous serial i/o peripherals on other embedded cont rollers. the receiver employs an advanced data sampling technique that ensures reliable communication and noise detection. hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. note MC9S08JM16 series devices operate at a higher voltage range (2.7 v to 5.5 v) and do not include stop1 mode . therefore, please disregard references to stop1.
chapter 14 serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 220 freescale semiconductor figure 14-1. MC9S08JM16 series block diag ram highlighting the sci blocks and pins ptc1/sda ptc0/scl v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta5, pta0 pte0/txd1 pte1/rxd1 ptd1/adp9/acmp? ptd0/adp8/acmp+ ptc5/rxd2 ptc4 ptc3/txd2 ptc2 port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic) serial peripheral interface module (spi1) user flash (in bytes) user ram (in bytes) on-chip ice and debug module (dbg) hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pu llup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if rising edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. pin contains integrated pullup device. 5. when pin functions as kbi (kbipen = 1) and associated pin is configured to enable the pullup device, kbedgn can be used to reco nfigure the pullup as a pulldown device. 2-channel timer/pwm module (tpm2) ptb5/kbip5/adp5 port b pte5/mosi1 pte4/miso1 pte6/spsck1 pte7/ss1 hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset v ssad v ddad v refh analog-to-digital converter (adc) 4-channel timer/pwm module (tpm1) ptd7 2 ptb4/kbip4/adp4 ptg3/kbip7 ptg2/kbip6 port g 8-channel, 12-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 v refl ptg4/xtal ptg5/extal irq/tpmclk rxd2 txd2 sda scl 6 kbipx kbipx tpmclk spsck1 ss1 miso1 mosi1 tpmclk tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 2 4 usb sie usb endpoint ram full speed usb transceiver usbdp usbdn miso2 ss2 spsck2 mosi2 ptb1/mosi2/adp1 ptb0/miso2/adp0 8-/16-bit real-time counter (rtc) ptb3/ss2 /adp3 ptb2/spsck2/adp2 tpm1chx 3 tpm2ch1 tpm2ch0 2 analog comparator (acmp) system usb 3.3 v voltage regulator v usb33 1024 acmpo acmp+ acmp? ptd2/kbip2/acmpo 8-/16-bit serial peripheral interface module (spi2) mc9s08jm8 = 8,192 MC9S08JM16 = 16,384 v ssosc
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 221 14.1.1 features features of sci module include: ? full-duplex, standard non-re turn-to-zero (nrz) format ? double-buffered transmitter and re ceiver with separate enables ? programmable baud rates (13-bit modulo divider) ? interrupt-driven or polled operation: ? transmit data register em pty and transmission complete ? receive data register full ? receive overrun, parity error, framing erro r, and noise error ? idle receiver detect ? active edge on receive pin ? break detect supporting lin ? hardware parity generation and checking ? programmable 8-bit or 9-bit character length ? receiver wakeup by idle-line or address-mark ? optional 13-bit break character generati on / 11-bit break character detection ? selectable transmitt er output polarity 14.1.2 modes of operation see section 14.3, ?functio nal description ,? for details concerning sci operation in these modes: ? 8- and 9-bit data modes ? stop mode operation ? loop mode ? single-wire mode
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 222 freescale semiconductor 14.1.3 block diagram figure 14-2 shows the transmitter portion of the sci. figure 14-2. sci transmitter block diagram h 8 7 6 5 4 3 2 1 0 l scid ? tx buffer (write-only) internal bus stop 11-bit transmit shift register start shift direction lsb 1 baud rate clock parity generation transmit control shift enable preamble (all 1s) break (all 0s) sci controls txd txd direction to txd pin logic loop control to receive data in to txd pin tx interrupt request loops rsrc tie tc tdre m pt pe tcie te sbk t8 txdir load from scixd txinv brk13
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 223 figure 14-3 shows the receiver portion of the sci. figure 14-3. sci receiver block diagram h 8 7 6 5 4 3 2 1 0 l scid ? rx buffer (read-only) internal bus stop 11-bit receive shift register start shift direction lsb from rxd pin rate clock rx interrupt request data recovery divide 16 baud single-wire loop control wakeup logic all 1s msb from transmitter error interrupt request parity checking by 16 rdrf rie idle ilie or orie fe feie nf neie pf loops peie pt pe rsrc wake ilt rwu m lbkdif lbkdie rxedgif rxedgie active edge detect rxinv lbkde rwuid
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 224 freescale semiconductor 14.2 register definition the sci has eight 8-bit registers to control baud ra te, select sci options, report sci status, and for transmit/receive data. refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all sci registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 14.2.1 sci baud rate regi sters (scixbdh, scixbdl) this pair of registers co ntrols the prescale diviso r for sci baud rate genera tion. to update the 13-bit baud rate setting [sbr12:sbr0], first writ e to scixbdh to buffer the high half of the new value and then write to scixbdl. the working value in scixbdh does not change until scixbdl is written. scixbdl is reset to a non-zero value, so after reset the baud rate genera tor remains disabled until the first time the receiver or transmitter is enabled (re or te bits in scixc2 are written to 1). 76543210 r lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 w r e s e t00000000 = unimplemented or reserved figure 14-4. sci baud rate register (scixbdh) table 14-1. scixbdh field descriptions field description 7 lbkdie lin break detect interrupt enable (for lbkdif) 0 hardware interrupts from lbkdif disabled (use polling). 1 hardware interrupt requested when lbkdif flag is 1. 6 rxedgie rxd input active edge interrupt enable (for rxedgif) 0 hardware interrupts from rxedgif disabled (use polling). 1 hardware interrupt requested when rxedgif flag is 1. 4:0 sbr[12:8] baud rate modulo divisor ? the 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in ta b l e 1 4 - 2 .
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 225 14.2.2 sci control register 1 (scixc1) this read/write register is used to contro l various optional features of the sci system. 76543210 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset00000100 figure 14-5. sci baud rate register (scixbdl) table 14-2. scixbdl field descriptions field description 7:0 sbr[7:0] baud rate modulo divisor ? these 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in ta b l e 1 4 - 1 . 76543210 r loops sciswai rsrc m wake ilt pe pt w r e s e t00000000 figure 14-6. sci control register 1 (scixc1) table 14-3. scixc1 field descriptions field description 7 loops loop mode select ? selects between loop back modes and normal 2-pin full-duplex modes. when loops = 1, the transmitter output is internally connected to the receiver input. 0 normal operation ? rxd and txd use separate pins. 1 loop mode or single-wire mode where transmitter output s are internally connected to receiver input. (see rsrc bit.) rxd pin is not used by sci. 6 sciswai sci stops in wait mode 0 sci clocks continue to run in wait mode so the sci c an be the source of an interrupt that wakes up the cpu. 1 sci clocks freeze while cpu is in wait mode. 5 rsrc receiver source select ? this bit has no meaning or effect unless the loops bit is set to 1. when loops = 1, the receiver input is internally connected to the txd pin and rsrc determines whether this connection is also connected to the transmitter output. 0 provided loops = 1, rsrc = 0 selects internal loop back mode and the sci does not use the rxd pins. 1 single-wire sci mode where the txd pin is connecte d to the transmitter output and receiver input. 4 m 9-bit or 8-bit mode select 0 normal ? start + 8 data bits (lsb first) + stop. 1 receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 226 freescale semiconductor 14.2.3 sci control register 2 (scixc2) this register can be read or written at any time. 3 wake receiver wakeup method select ? refer to section 14.3.3.2, ?recei ver wakeup operation ? for more information. 0 idle-line wakeup. 1 address-mark wakeup. 2 ilt idle line type select ? setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. refer to section 14.3.3.2.1, ?idle-line wakeup ? for more information. 0 idle character bit count starts after start bit. 1 idle character bit count starts after stop bit. 1 pe parity enable ? enables hardware parity generation and checking. when parity is enabled, the most significant bit (msb) of the data character (eighth or ninth data bit) is treat ed as the parity bit. 0 no hardware parity generation or checking. 1 parity enabled. 0 pt parity type ? provided parity is enabled (pe = 1), this bit selects even or odd parity. odd parity means the total number of 1s in the data character, including the parity bi t, is odd. even parity means the total number of 1s in the data character, including the parity bit, is even. 0 even parity. 1 odd parity. 76543210 r tie tcie rie ilie te re rwu sbk w reset00000000 figure 14-7. sci control register 2 (scixc2) table 14-4. scixc2 field descriptions field description 7 tie transmit interrupt enable (for tdre) 0 hardware interrupts from tdre disabled (use polling). 1 hardware interrupt requested when tdre flag is 1. 6 tcie transmission complete interrupt enable (for tc) 0 hardware interrupts from tc disabled (use polling). 1 hardware interrupt requested when tc flag is 1. 5 rie receiver interrupt enable (for rdrf) 0 hardware interrupts from rdrf disabled (use polling). 1 hardware interrupt requested when rdrf flag is 1. 4 ilie idle line interrupt enable (for idle) 0 hardware interrupts from idle disabled (use polling). 1 hardware interrupt requested when idle flag is 1. table 14-3. scixc1 field descriptions (continued) field description
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 227 14.2.4 sci status register 1 (scixs1) this register has eight read-only st atus flags. writes have no effect. special software sequences (which do not involve writing to this register) are used to clear these status flags. 3 te transmitter enable 0 transmitter off. 1 transmitter on. te must be 1 in order to use the sci transmitter. when te = 1, the sci forces the txd pin to act as an output for the sci system. when the sci is configured for single-wire operation (loops = rsrc = 1), txdir controls the direction of traffic on the single sci communication line (txd pin). te also can be used to queue an idle character by writing te = 0 then te = 1 while a transmission is in progress. refer to section 14.3.2.1, ?send break and queued idle ? for more details. when te is written to 0, the transmitt er keeps control of the port txd pi n until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose i/o pin. 2 re receiver enable ? when the sci receiver is off, the rxd pin reverts to being a general-purpose port i/o pin. if loops = 1 the rxd pin reverts to being a general-purpose i/o pin even if re = 1. 0 receiver off. 1 receiver on. 1 rwu receiver wakeup control ? this bit can be written to 1 to place the sci receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. the wakeup condition is either an idle line between messages (wake = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character (wake = 1, address-mark wakeup). application software sets rwu and (normally) a selected hardware condition automatically clears rwu. refer to section 14.3.3.2, ?rec eiver wakeup operation ? for more details. 0 normal sci receiver operation. 1 sci receiver in standby waiting for wakeup condition. 0 sbk send break ? writing a 1 and then a 0 to sbk queues a break character in the transmit data stream. additional break characters of 10 or 11 (13 or 14 if brk13 = 1) bit times of logic 0 are queued as long as sbk = 1. depending on the timing of the set and clear of sbk relati ve to the information currently being transmitted, a second break character may be queued before software clears sbk. refer to section 14.3.2.1, ?send break and queued idle ? for more details. 0 normal transmitter operation. 1 queue break character(s) to be sent. 76543210 r tdre tc rdrf idle or nf fe pf w r e s e t11000000 = unimplemented or reserved figure 14-8. sci status register 1 (scixs1) table 14-4. scixc2 field descriptions (continued) field description
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 228 freescale semiconductor table 14-5. scixs1 field descriptions field description 7 tdre transmit data register empty flag ? tdre is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving r oom for a new character in the buffer. to clear tdre, read scixs1 with tdre = 1 and then write to the sci data register (scixd). 0 transmit data register (buffer) full. 1 transmit data register (buffer) empty. 6 tc transmission complete flag ? tc is set out of reset and when tdre = 1 and no data, preamble, or break character is being transmitted. 0 transmitter active (sending data, a preamble, or a break). 1 transmitter idle (transmi ssion activity complete). tc is cleared automatically by read ing scixs1 with tc = 1 and then doing one of the following three things: ? write to the sci data register (scixd) to transmit new data ? queue a preamble by changing te from 0 to 1 ? queue a break character by writing 1 to sbk in scixc2 5 rdrf receive data register full flag ? rdrf becomes set when a character transfers from the receive shifter into the receive data register (scixd). to clear rdrf, read scixs1 with rdrf = 1 and then read the sci data register (scixd). 0 receive data register empty. 1 receive data register full. 4 idle idle line flag ? idle is set when the sci receive line becomes idle for a full character time after a period of activity. when ilt = 0, the receiver starts counting idle bit times after the start bit. so if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the m control bit) needed for the receiver to detect an idle line. when ilt = 1, the receiver doesn?t start counting idle bit times until after the stop bit. so th e stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. to clear idle, read scixs1 with idle = 1 and then read the sci data register (scixd). after idle has been cleared, it cannot become set again until after a new character has been received and rdrf has been set. idle will get set only once even if the receive line remains idle for an extended period. 0 no idle line detected. 1 idle line was detected. 3 or receiver overrun flag ? or is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from scixd yet. in this case, the new character (and all associated error information) is lost bec ause there is no room to move it into scixd. to clear or, read scixs1 with or = 1 and then read the sci data register (scixd). 0 no overrun. 1 receive overrun (new sci data lost). 2 nf noise flag ? the advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. if an y of these samples disagrees with the rest of the samples within any bit time in the frame, the flag nf will be set at the same time as the flag rdrf gets set for the character. to clear nf, read scixs1 and then read the sci data register (scixd). 0 no noise detected. 1 noise detected in the received character in scixd.
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 229 14.2.5 sci status register 2 (scixs2) this register has one read-only status flag. 1 fe framing error flag ? fe is set at the same time as rdrf when the receiver detects a logic 0 where the stop bit was expected. this suggests the receiver was not properly aligned to a character frame. to clear fe, read scixs1 with fe = 1 and then read the sci data register (scixd). 0 no framing error detected. this does not guarantee the framing is correct. 1 framing error. 0 pf parity error flag ? pf is set at the same time as rdrf when parity is enabled (pe = 1) and the parity bit in the received character does not agree with the expected parity value. to clear pf, read scixs1 and then read the sci data register (scixd). 0 no parity error. 1 parity error. 76543210 r lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf w r e s e t00000000 = unimplemented or reserved figure 14-9. sci status register 2 (scixs2) table 14-6. scixs2 field descriptions field description 7 lbkdif lin break detect interrupt flag ? lbkdif is set when the lin break detect circuitry is enabled and a lin break character is detected. lbkdif is cleared by writing a ?1? to it. 0 no lin break character has been detected. 1 lin break character has been detected. 6 rxedgif rxd pin active edge interrupt flag ? rxedgif is set when an active edge (falling if rxinv = 0, rising if rxinv=1) on the rxd pin occurs. rxedgif is cleared by writing a ?1? to it. 0 no active edge on the receive pin has occurred. 1 an active edge on the receive pin has occurred. 4 rxinv 1 receive data inversion ? setting this bit reverses the polarity of the received data input. 0 receive data not inverted 1 receive data inverted 3 rwuid receive wake up idle detect ? rwuid controls whether the idle charac ter that wakes up the receiver sets the idle bit. 0 during receive standby state (rwu = 1), the idle bit does not get set upon detection of an idle character. 1 during receive standby state (rwu = 1), the idle bit gets set upon detection of an idle character. 2 brk13 break character generation length ? brk13 is used to select a longer transmitted break character length. detection of a framing error is not affected by the state of this bit. 0 break character is transmitted with length of 10 bit times (11 if m = 1) 1 break character is transmitted with length of 13 bit times (14 if m = 1) table 14-5. scixs1 field descriptions (continued) field description
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 230 freescale semiconductor when using an internal oscillator in a lin system, it is necessary to raise the break detection threshold by one bit time. under the worst case timing conditions allowed in lin, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slav e which is running 14% faster than the master. this would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. when the lbkde bit is set, framing errors are inhibited and the break detectio n threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a lin break symbol. 14.2.6 sci control register 3 (scixc3) 1 lbkde lin break detection enable ? lbkde is used to select a longer break character detection length. while lbkde is set, framing error (fe) and receive data regi ster full (rdrf) flags are prevented from setting. 0 break character is detected at length of 10 bit times (11 if m = 1). 1 break character is detected at length of 11 bit times (12 if m = 1). 0 raf receiver active flag ? raf is set when the sci receiver detects the beginning of a valid start bit, and raf is cleared automatically when the receiver detects an idle line. this status flag can be used to check whether an sci character is being received before instructing the mcu to go to stop mode. 0 sci receiver idle waiting for a start bit. 1 sci receiver active (rxd input not idle). 1 setting rxinv inverts the rxd input for all cases: data bits, start and stop bits, break, and idle. 76543210 rr8 t8 txdir txinv orie neie feie peie w r e s e t00000000 = unimplemented or reserved figure 14-10. sci control register 3 (scixc3) table 14-7. scixc3 field descriptions field description 7 r8 ninth data bit for receiver ? when the sci is configured for 9-bit data (m = 1), r8 can be thought of as a ninth receive data bit to the left of the msb of the buffered da ta in the scixd register. when reading 9-bit data, read r8 before reading scixd because reading scixd complete s automatic flag clearing sequences which could allow r8 and scixd to be overwritten with new data. 6 t8 ninth data bit for transmitter ? when the sci is configured for 9-bit data (m = 1), t8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the scixd regi ster. when writing 9-bit data, the entire 9-bit value is transferred to the sci shift register after sc ixd is written so t8 must be written (if it needs to change from its previous value) before scixd is written. if t8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time scixd is written. 5 txdir txd pin direction in single-wire mode ? when the sci is configured for single-wire half-duplex operation (loops = rsrc = 1), this bit determines t he direction of data at the txd pin. 0 txd pin is an input in single-wire mode. 1 txd pin is an output in single-wire mode. table 14-6. scixs2 field descriptions (continued) field description
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 231 14.2.7 sci data register (scixd) this register is actually two separate registers. r eads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. reads and wr ites of this register are also involved in the automatic flag clearing mechanisms for the sci status flags. 14.3 functional description the sci allows full-duplex, as ynchronous, nrz serial communica tion among the mcu and remote devices, including other mcus. the sc i comprises a baud rate generator, transmitter, and receiver block. the transmitter and receiver opera te independently, although they use the same baud rate generator. during normal operation, the mcu monitors the status of the sci, writes the data to be transmitted, and processes received data. the following desc ribes each of the blocks of the sci. 14.3.1 baud rate generation as shown in figure 14-12 , the clock source for the sci baud rate generator is the bus-rate clock. 4 txinv 1 transmit data inversion ? setting this bit reverses the pola rity of the transmitted data output. 0 transmit data not inverted 1 transmit data inverted 3 orie overrun interrupt enable ? this bit enables the overrun flag (or) to generate hardware interrupt requests. 0 or interrupts disabled (use polling). 1 hardware interrupt requested when or = 1. 2 neie noise error interrupt enable ? this bit enables the noise flag (nf) to generate hardware interrupt requests. 0 nf interrupts disabled (use polling). 1 hardware interrupt requested when nf = 1. 1 feie framing error interrupt enable ? this bit enables the framing error flag (fe) to generate hardware interrupt requests. 0 fe interrupts disabled (use polling). 1 hardware interrupt requested when fe = 1. 0 peie parity error interrupt enable ? this bit enables the parity error flag (pf) to generate hardware interrupt requests. 0 pf interrupts disabled (use polling). 1 hardware interrupt requested when pf = 1. 1 setting txinv inverts the txd output for all cases: data bits, start and stop bits, break, and idle. 76543210 rr 7r 6r 5r 4r 3r 2r 1r 0 wt 7t 6t 5t 4t 3t 2t 1t 0 r e s e t00000000 figure 14-11. sci data register (scixd) table 14-7. scixc3 field descriptions (continued) field description
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 232 freescale semiconductor figure 14-12. sci baud rate generation sci communications require the transmitter and re ceiver (which typically derive baud rates from independent clock sources) to use the same baud rate. allowed tolera nce on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. the mcu resynchronizes to bit boundari es on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. for a freescale semiconductor sci system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about 4.5 percent for 8-bit data format and about 4 percent for 9-bit data format. alt hough baud rate modulo divider settings do not always produce baud rates that exactly match st andard rates, it is normally possi ble to get within a few percent, which is acceptable for reliable communications. 14.3.2 transmitter functional description this section describes the overall block diagram for th e sci transmitter, as well as specialized functions for sending break and idle characters. the transmitter block diagram is shown in figure 14-2 . the transmitter output (txd) idle state defaults to logic high (txinv = 0 following reset). the transmitter output is inverted by setting txinv = 1. the transmitter is enabled by se tting the te bit in scixc2. this queues a preamble character that is one full character fr ame of the idle state. th e transmitter then remains idle until data is available in the tr ansmit data buffer. progr ams store data into the transmit data buffer by writing to the sci data register (scixd). the central element of the sci transmit ter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the m control bit. for th e remainder of this section, we will assume m = 0, selecting the normal 8-bi t data mode. in 8-bit data m ode, the shift register holds a start bit, eight data bits, and a stop bit. when the transmit shift register is available for a new sci character, the value waiting in the transmit data register is transfer red to the shift register (synchronized with the ba ud rate clock) and the transmit data register empt y (tdre) status flag is set to indicate another character may be written to the transmit data buffer at scixd. if no new character is waiting in th e transmit data buffer after a stop bit is shifted out the txd pin, the transmitter sets the transmit comp lete flag and enters an idle m ode, with txd high, waiting for more characters to transmit. sbr12:sbr0 divide by tx baud rate rx sampling clock (16 baud rate) baud rate generator off if [sbr12:sbr0] = 0 busclk baud rate = busclk [sbr12:sbr0] 16 16 modulo divide by (1 through 8191)
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 233 writing 0 to te does not immediately release the pin to be a general-pur pose i/o pin. any tr ansmit activity that is in progress must first be completed. this includes data characters in progress, queued idle characters, and queued break characters. 14.3.2.1 send break and queued idle the sbk control bit in scixc2 is used to send break characters which were originally used to gain the attention of old teletype receivers. break characters are a full character time of logic 0 (10 bit times including the start and stop bits). a longer break of 13 bit times can be enabled by setting brk13 = 1. normally, a program would wait for tdre to become se t to indicate the last ch aracter of a message has moved to the transmit shifter, then write 1 and then write 0 to the sbk bit. this action queues a break character to be sent as soon as the shifter is avai lable. if sbk is st ill 1 when the queue d break moves into the shifter (synchronized to the baud ra te clock), an additional break char acter is queued. if the receiving device is another freescale semiconductor sci, the break characters will be received as 0s in all eight data bits and a framing error (fe = 1) occurs. when idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. normally, a program would wait for tdre to become set to indicate the last character of a message has moved to the transmit shifte r, then write 0 and then write 1 to the te bit. this action queues an idle ch aracter to be sent as soon as the shifter is available. as long as the character in the shifter does not finish while te = 0, th e sci transmitter never actually re leases control of the txd pin. if there is a possibility of the shifter finishing while te = 0, set the general-purpose i/o controls so the pin that is shared with txd is an output driving a logic 1. this ensures that the txd line will look like a normal idle line even if the sci loses control of the port pin between writing 0 and then 1 to te. the length of the break character is affected by the brk13 and m bits as shown below. 14.3.3 receiver functional description in this section, the r eceiver block diagram ( figure 14-3 ) is used as a guide for the overall receiver functional description. next, the data sampling technique used to reconstruc t receiver data is described in more detail. finally, two variations of the receiver wakeup function are explained. the receiver input is inverted by setting rxinv = 1. the receiver is enabled by setting the re bit in scixc2. character frames consist of a start bit of logic 0, eight (or nine ) data bits (lsb first), and a stop bit of logic 1. for information ab out 9-bit data mode, refer to section 14.3.5.1, ?8- and 9-bit data modes .? for the remainder of this discussion, we assume the sci is confi gured for normal 8-bit data mode. after receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive da ta register and the receive data register full (rdrf) table 14-8. break character length brk13 m break character length 0 0 10 bit times 0 1 11 bit times 1 0 13 bit times 1 1 14 bit times
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 234 freescale semiconductor status flag is set. if rdrf was already se t indicating the receive data register (buffer) was already full, the overrun (or) status flag is set and the new data is lost. because the sci re ceiver is double-buffered, the program has one full character time after rdrf is set before the data in the receive data buffer must be read to avoid a receiver overrun. when a program detects that the receiv e data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user?s program that handles receive data. refer to section 14.3.4, ?interrupts and status flags ,? for more details about flag clearing. 14.3.3.1 data sampling technique the sci receiver uses a 16 baud rate clock for sampling. the receiv er starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the rxd serial data input pin. a falling edge is defined as a logic 0 sample after thre e consecutive logic 1 samples. the 16 baud rate clock is used to divide the bit time into 16 segments labeled rt1 through rt16. when a fa lling edge is located, three more samples are taken at rt3, rt5, and rt7 to make sure this was a real start bit a nd not merely noise. if at least two of these three samples ar e 0, the receiver assumes it is s ynchronized to a receive character. the receiver then samples each bi t time, including the start and stop bits, at rt8, rt9, and rt10 to determine the logic level for that bit. the logic level is interpreted to be that of the majority of the samples taken during the bit time. in th e case of the start bit, the bit is assumed to be 0 if at least two of the samples at rt3, rt5, and rt7 are 0 even if one or all of the samples taken at rt8, rt9, and rt10 are 1s. if any sample in any bit time (including th e start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (nf) will be set wh en the received character is transferred to the receive data buffer. the falling edge detection l ogic continuously looks for fall ing edges, and if an edge is detected, the sample clock is resynchronized to bit times. this improves the reliability of the receiver in the presence of noise or mismatched baud rates. it does not improve worst case analysis because some characters do not have any extra falling edges anywhe re in the character frame. in the case of a framing error, pr ovided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. in the case of a framing error, the receiver is inhibited from receiving any new charac ters until the framing error flag is cleared. the receive shift register continues to f unction, but a complete character cannot transfer to the receive data buffer if fe is still set. 14.3.3.2 receiver wakeup operation receiver wakeup is a hardware mech anism that allows an sci receiver to ignore the characters in a message that is intended for a different sci receiver. in such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (rwu) control bit in scixc2. when rwu bit is set, the status flags associated with th e receiver (with the exception of the idle bit, idle, when rwuid bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 235 message characters. at the end of a message, or at the beginning of the ne xt message, all receivers automatically force rwu to 0 so all receivers wake up in time to look at the first character(s) of the next message. 14.3.3.2.1 idle-line wakeup when wake = 0, the receiver is configured for idle-line wakeup. in this mode, rwu is cleared automatically when the receiver detect s a full character time of the idle-l ine level. the m control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle ar e needed to constitute a full character time (10 or 11 bit times becaus e of the start and stop bits). when rwu is one and rwuid is ze ro, the idle condition that wakes up the receiver does not set the idle flag. the receiver wakes up and waits for the first da ta character of the next message which will set the rdrf flag and generate an interrupt if enabled. when rwuid is one, any idle condition sets the idle flag and generates an interrupt if enabled, regardless of whether rwu is zero or one. the idle-line type (ilt) control bit se lects one of two ways to detect an idle line. when ilt = 0, the idle bit counter starts after the start bit so the stop bit a nd any logic 1s at the end of a character count toward the full character time of idle. when ilt = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 14.3.3.2.2 address-mark wakeup when wake = 1, the receiver is configured for a ddress-mark wakeup. in this mode, rwu is cleared automatically when the receiver detect s a logic 1 in the most significant bi t of a received character (eighth bit in m = 0 mode and ninth bit in m = 1 mode). address-mark wakeup allows messages to contain idle characters but re quires that the msb be reserved for use in address frames. the logic 1 msb of an address frame clears the rwu bit before the stop bit is received and sets the rdrf flag. in this case the ch aracter with the msb set is received even though the receiver was sleeping during most of this character time. 14.3.4 interrupts and status flags the sci system has three se parate interrupt vectors to reduce the amount of softwa re needed to isolate the cause of the interrupt. one interrupt vector is associated with th e transmitter for tdre and tc events. another interrupt vector is associ ated with the receiver for rdrf, idle, rxedgif and lbkdif events, and a third vector is used for or, nf, fe, and pf error conditions. each of these ten interrupt sources can be separately masked by local interr upt enable masks. the flags can still be polled by software when the local masks are cleared to disable gene ration of hardware interrupt requests. the sci transmitter has two status fl ags that optionally can generate hard ware interrupt re quests. transmit data register empty (tdre) indicates when there is room in the transmit data buffer to write another transmit character to scixd. if the transmit interrupt enable (tie) bit is set, a hardware interrupt will be requested whenever tdre = 1. transmit complete (t c) indicates that the transmitter is finished transmitting all data, preamble , and break characters and is idle with txd at the inactive level. this flag is often used in systems with modems to determine when it is safe to turn off the modem. if the transmit complete interrupt enable (tcie) bit is set, a ha rdware interrupt will be requested whenever tc = 1.
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 236 freescale semiconductor instead of hardware interrupts, soft ware polling may be used to monitor the tdre and tc status flags if the corresponding tie or tcie local interrupt masks are 0s. when a program detects that the receiv e data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf flag is cleared by reading scixs1 while rdrf = 1 and then reading scixd. when polling is used, this sequence is naturally satisfied in the normal course of the user program. if hardware interrupts are used, scixs1 mu st be read in the interrupt servi ce routine (isr). normally, this is done in the isr anyway to check for receive erro rs, so the sequence is automatically satisfied. the idle status flag includes logic th at prevents it from ge tting set repeatedly when the rxd line remains idle for an extended period of time . idle is cleared by reading scixs1 while idle = 1 and then reading scixd. after idle has been cleared, it cannot become set again until the receiver has received at least one new character and has set rdrf. if the associated error was detected in the received character that caused rdrf to be set, the error flags ? noise flag (nf), framing error (fe) , and parity error flag (pf) ? get set at the same time as rdrf. these flags are not set in overrun cases. if rdrf was already set when a new character is rea dy to be transferred from the receive shifter to the receive data buffer, the overrun (or) flag gets set inst ead the data along with any associated nf, fe, or pf condition is lost. at any time, an active edge on th e rxd serial data input pin causes the rxedgif flag to set. the rxedgif flag is cleared by writing a ?1? to it. this function doe s depend on the receiver being enabled (re = 1). 14.3.5 additional sci functions the following sections descri be additional sci functions. 14.3.5.1 8- and 9-bit data modes the sci system (transmitter and receiver) can be conf igured to operate in 9-bi t data mode by setting the m control bit in scixc1. in 9-bit m ode, there is a ninth data bit to th e left of the msb of the sci data register. for the transmit data buffer, this bit is stored in t8 in scixc3. for the receiver, the ninth bit is held in r8 in scixc3. for coherent writes to the transmit data buffer, write to the t8 bit before writing to scixd. if the bit value to be transm itted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to t8 again. when data is transferred from the transmit data buffer to the transmit shifter, the value in t8 is copied at the same time data is transferred from scixd to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. in custom protocols, the ninth bit can also serve as a software-controlled marker.
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 237 14.3.5.2 stop mode operation during all stop modes, clocks to the sci module are halted. in stop1 and stop2 modes, all sci regist er data is lost and must be re-initialized upon reco very from these two stop modes. no sci module regi sters are affected in stop3 mode. the receive input active edge detect circuit is still active in stop3 mode, but not in stop2. an active edge on the receive input brings the cpu out of stop3 mode if the interrupt is not masked (rxedgie = 1). note, because the clocks are halted, the sci module will resume operation upon exit from stop (only in stop3 mode). software must ensure stop mode is not entered while there is a character being transmitted out of or received into the sci module. 14.3.5.3 loop mode when loops = 1, the rsrc bit in the same regist er chooses between l oop mode (rsrc = 0) or single-wire mode (rsrc = 1). loop mode is someti mes used to check software, independent of connections in the external system, to help isolate system pr oblems. in this mode, the transmitter output is internally connected to the receiver input and the rxd pin is not used by the sci, so it reverts to a general-purpose port i/o pin. 14.3.5.4 single-wire operation when loops = 1, the rsrc bit in the same regist er chooses between l oop mode (rsrc = 0) or single-wire mode (rsrc = 1). single- wire mode is used to implemen t a half-duplex serial connection. the receiver is internally connected to the transmitter output and to the txd pin. the rxd pin is not used and reverts to a general-purpose port i/o pin. in single-wire mode, the tx dir bit in scixc3 controls the direction of serial data on the txd pin. when txdir = 0, the txd pin is an input to the sci receiver and the transmit ter is temporarily disconnected from the txd pin so an external de vice can send serial data to the receiver. when txdir = 1, the txd pin is an output driven by the transmitter. in single-wi re mode, the internal l oop back connection from the transmitter to the receiver causes the receiver to receive characte rs that are sent out by the transmitter.
serial communications interface (s08sciv4) MC9S08JM16 series data sheet, rev. 2 238 freescale semiconductor
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 239 chapter 15 16-bit serial peripheral interface (s08spi16v1) 15.1 introduction the 8- or 16-bit selectable serial peripheral inte rface (spi) module provides for full-duplex, synchronous, serial communication between the mcu and peripheral devices. thes e peripheral devices can include other microcontrollers, analog-to-digital converter s, shift registers, sensors, memories, etc. the spi runs at a baud rate up to the bus clock divi ded by two in master mode and up to the bus clock divided by four in slave mode. softwa re can poll the status flags, or spi operation can be interrupt driven. the spi also supports a data length of 8 or 16 bits and includes a hardware match feature for the receive data buffer. the MC9S08JM16 series have two serial peripheral interface modules (spi1 and spi2). the four pins associated with spi functionality are shared with ptb[3:0] and pte[7:4]. see appendix a, ?electrical characteristics ,? for spi electrical parametric information. 15.1.1 spi port configuration information by default, the input filters on the spi port pins will be en abled (spixfe=1), which restricts the spi data rate to 6 mhz, but protects the spi from noise during data tr ansfers.to configure the spi at a baud rate of 6 mhz or greater, the input filters on the spi port pins must be disabled by clearing the spixfe in sopt2. and also enable the high output drive strength selection on the affected spi port pins.
chapter 15 16-bit serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 240 freescale semiconductor figure 15-1. MC9S08JM16 series block diag ram highlighting the spi blocks and pins ptc1/sda ptc0/scl v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta5, pta0 pte0/txd1 pte1/rxd1 ptd1/adp9/acmp? ptd0/adp8/acmp+ ptc5/rxd2 ptc4 ptc3/txd2 ptc2 port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic) 8-/16-bit serial peripheral interface module (spi16) user flash (in bytes) user ram (in bytes) on-chip ice and debug module (dbg) mc9s08jm60 = 60,912 hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if risi ng edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. pin contains integrated pullup device. 5. when pin functions as kbi (kbipen = 1) an d associated pin is configured to enable the pullup device, kbedgn can be used to rec onfigure the pullup as a pulldown device. 2-channel timer/pwm module (tpm2) ptb5/kbip5/adp5 port b pte5/mosi1 pte4/miso1 pte6/spsck1 pte7/ss1 hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset v ssad v ddad v refh analog-to-digital converter (adc) 4-channel timer/pwm module (tpm1) ptd7 2 ptb4/kbip4/adp4 ptg3/kbip7 ptg2/kbip6 port g 12-channel, 12-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 mc9s08jm32 = 32,768 v refl ptg4/xtal ptg5/extal irq/tpmclk rxd2 txd2 sda scl 6 kbipx kbipx tpmclk spsck1 ss1 miso1 mosi1 tpmclk tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 2 4 usb sie usb endpoint ram full speed usb transceiver usbdp usbdn miso2 ss2 spsck2 mosi2 ptb1/mosi2/adp1 ptb0/miso2/adp0 8-/16-bit serial peripheral interface module (spi2) real-time counter (rtc) ptb3/ss2 /adp3 ptb2/spsck2/adp2 tpm1chx 3 tpm2ch1 tpm2ch0 2 analog comparator (acmp) system usb 3.3 v voltage regulator v usb33 mc9s08jm60 = 4096 mc9s08jm32 = 2048 acmpo acmp+ acmp? ptd2/kbip2/acmpo v ssosc
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 241 figure 15-2. spi module quick start mstr cpol cpha ssoe lsbfe modfen bidiroe spimode spiswai spc0 spmie additional configuration options. sppr0 spr2 spr1 spr0 sppr2 sppr1 baud rate = (busclk/sppr[2:0])/spr2[2:0] bit 15 bit 7 module initialization (slave): write: spixc1 to configure inter rupts, set primary spi options, slave mode select, and system enable. write: spixc2 to configure optional spi feat ures, hardware match interrupt enable, and 8- or 16-bit data transmission length write: spixmh:spixml to set hardware compar e value that triggers spmf (optional) when value in receive data buffer equals this value. module initialization (master): write: spixc1 to configure interrupts, set primary spi options, master mode select, and system enable. write: spixc2 to configure optional spi feat ures, hardware match interrupt enable, and 8- or 16-bit data transmission length write: spixbr to set baud rate write: spixmh:spixml to set hardware compare value that triggers spmf (optional) when value in receive data buffer equals this value. module use: after spi master initiates transfer by checking that sptef = 1 and then writing data to spidh/l: wait for sprf, then read from spidh/l wait for sptef, then write to spidh/l data transmissions can be 8- or 16-bits long, and mode f ault detection can be enabled for master mode in cases where more than one spi device might become a master at the same time. also, some applications may utilize the receive data buffer hardware match feature to trigger specific actions, su ch as when command data can be sent through the spi or to indicate the end of an spi transmission. spixc1 spixc2 spixbr spixdh spixdl spie spe sptie module/interrupt enables and configuration bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spixmh hardware match value bit 15 bit 7 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 modf sptef spixs sprf spmf spixml
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 242 freescale semiconductor 15.1.2 features the spi includes these distinctive features: ? master mode or slave mode operation ? full-duplex or single-w ire bidirectional mode ? programmable transmit bit rate ? double-buffered transmit a nd receive data register ? serial clock phase and polarity options ? slave select output ? mode fault error flag with cpu interrupt capability ? control of spi operation during wait mode ? selectable msb-first or lsb-first shifting ? programmable 8- or 16-bit data transmission length ? receive data buffer hardware match feature 15.1.3 modes of operation the spi functions in three modes, run, wait, and stop. ? run mode this is the basic mode of operation. ? wait mode spi operation in wait mode is a configurable low power mode, controlled by the spiswai bit located in the spixc2 register. in wait mode, if the spiswai bit is clear, the spi operates like in run mode. if the spiswai bit is set, the spi goes into a power conservative state, with the spi clock generation turned off. if the spi is configur ed as a master, any transm ission in progress stops, but is resumed after cpu goes into run mode. if the spi is configured as a slave, reception and transmission of a byte conti nues, so that the slave stays synchronized to the master. ? stop mode the spi is inactive in stop3 mode for reduced power consumption. if the spi is configured as a master, any transmission in progress stops, but is resumed after the cpu goes into run mode. if the spi is configured as a slave, reception and transmission of a data continues, so that the slave stays synchronized to the master. the spi is completely disabled in all other stop m odes. when the cpu wakes fr om these stop modes, all spi register content will be reset. this is a high level description on ly, detailed descriptions of opera ting modes are contained in section section 15.4.9, ?low power mode options .? 15.1.4 block diagrams this section includes block diagrams showing spi system c onnections, the internal organization of the spi module, and the spi clock dividers that control the master mode bit rate.
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 243 15.1.4.1 spi system block diagram figure 15-3 shows the spi modules of two mcus connected in a master-slave arrangement. the master device initiates all spi data transfers. during a transfer, the master sh ifts data out (on th e mosi pin) to the slave while simultaneously shifting data in (on the miso pin) from the slave. the transfer effectively exchanges the data that was in the spi shift registers of the two spi systems. the spsck signal is a clock output from the master and an input to the slave. the slave device must be selected by a low level on the slave select input (ss pin). in this system, the mast er device has c onfigured its ss pin as an optional slave select output. figure 15-3. spi system connections 15.1.4.2 spi module block diagram figure 15-4 is a block diagram of the spi module. the central element of th e spi is the spi shift register. data is written to the double-buffe red transmitter (write to spixdh:spixdl) and gets transferred to the spi shift register at the st art of a data transfer. after shifting in 8 or 16 bits (as de termined by spimode bit) of data, the data is transferred into the double- buffered receiver where it can be read (read from spixdh:spixdl). pin multiplexing logic controls c onnections between mcu pi ns and the spi module. when the spi is configured as a master, the clock out put is routed to the spsc k pin, the shifter output is routed to mosi, and the shifter input is routed from the miso pin. when the spi is configured as a slave, the spsck pin is routed to the clock i nput of the spi, the shifter output is routed to miso, and the shifte r input is routed from the mosi pin. in the external spi system, simply connect all spsck pins to each other, all miso pins together, and all mosi pins together. peripheral devices often use slightly different names for these pins. spi shifter clock generator spi shifter ss spsck miso mosi ss spsck miso mosi master slave 8 or 16 bits 8 or 16 bits
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 244 freescale semiconductor figure 15-4. spi module block diagram 15.2 external signal description the spi optionally shares four port pi ns. the function of these pins depe nds on the settings of spi control bits. when the spi is disabled (spe = 0), these four pins re vert to being general-pur pose port i/o pins that are not controlled by the spi. 15.2.1 spsck ? spi serial clock when the spi is enabled as a slave, this pin is the serial clock input. wh en the spi is enabled as a master, this pin is the serial clock output. spie spi shift register shift clock shift direction rx buffer full tx buffer empty shift out shift in enable spi system clock logic clock generator bus rate clock master/slave mode select mode fault detection master clock slave clock spi interrupt request pin control m s master/ slave mosi (momi) miso (siso) spsck ss m s s m modf spe lsbfe mstr sprf sptef sptie modfen ssoe spc0 bidiroe spibr tx buffer (write spixdh:spixdl) rx buffer (read spixdh:spixdl) 8 or 16 bit mode spimode 16-bit comparator spmf spmie spixmh:spixml 16-bit latch
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 245 15.2.2 mosi ? master data out, slave data in when the spi is enabled as a master and spi pin cont rol zero (spc0) is 0 (not bidirectional mode), this pin is the serial data output. when the spi is enabled as a slave and spc 0 = 0, this pin is the serial data input. if spc0 = 1 to select single-wire bidirectional mode, and master m ode is selected, this pin becomes the bidirectional data i/o pin (mom i). also, the bidirecti onal mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bidiroe = 1). if spc0 = 1 and slave mode is selected, this pin is not used by the spi and reverts to being a gene ral-purpose port i/o pin. 15.2.3 miso ? master da ta in, slave data out when the spi is enabled as a master and spi pin cont rol zero (spc0) is 0 (not bidirectional mode), this pin is the serial data input. when the spi is enable d as a slave and spc0 = 0, this pin is the serial data output. if spc0 = 1 to select single-wire bidirectional mode, and slave mode is se lected, this pin becomes the bidirectional data i/o pin (siso) and the bidirectional mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bid iroe = 1). if spc0 = 1 and ma ster mode is selected, this pin is not used by the spi and reve rts to being a general-purpose port i/o pin. 15.2.4 ss ? slave select when the spi is enabled as a slave, this pin is the lo w-true slave select input. wh en the spi is enabled as a master and mode fault enable is off (modfen = 0), this pin is not us ed by the spi and reverts to being a general-purpose port i/o pin. when the spi is enabled as a master and modf en = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (ssoe = 0) or as the slave select output (ssoe = 1). 15.3 register definition the spi has eight 8-bit registers to select spi options, control baud rate, report spi status, hold an spi data match value, and for transmit/receive data. refer to the direct-page register summ ary in the memory chapter of this data sheet for the absolute address assignments for all spi registers. this section refers to register s and control bits only by their names, and a freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 15.3.1 spi control register 1 (spixc1) this read/write register includes the spi enable control, interrupt enables, and configuration options. 76543210 r spie spe sptie mstr cpol cpha ssoe lsbfe w r e s e t00000100 figure 15-5. spi control register 1 (spixc1)
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 246 freescale semiconductor 15.3.2 spi control register 2 (spixc2) this read/write register is used to control optional feat ures of the spi system. bits 6 and 5 are not implemented and always read 0. table 15-1. spixc1 field descriptions field description 7 spie spi interrupt enable (for sprf and modf) ? this is the interrupt enable for spi receive buffer full (sprf) and mode fault (modf) events. 0 interrupts from sprf and modf inhibited (use polling) 1 when sprf or modf is 1, request a hardware interrupt 6 spe spi system enable ? this bit enables the spi system and dedicates the spi port pins to spi system functions. if spe is cleared, spi is disa bled and forced into idle state, and all stat us bits in the spixs register are reset. 0 spi system inactive 1 spi system enabled 5 sptie spi transmit interrupt enable ? this is the interrupt enable bit for spi transmit buffer empty (sptef). 0 interrupts from sptef inhibited (use polling) 1 when sptef is 1, hardware interrupt requested 4 mstr master/slave mode select ? this bit selects master or slave mode operation. 0 spi module configured as a slave spi device 1 spi module configured as a master spi device 3 cpol clock polarity ? this bit selects an inverted or non-inverted spi clock. to transmit data between spi modules, the spi modules must have identical cpol values. this bit effectively places an inverter in series with th e clock signal from a master spi or to a slave spi device. refer to section 15.4.5, ?spi clock formats ? for more details. 0 active-high spi clock (idles low) 1 active-low spi clock (idles high) 2 cpha clock phase ? this bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. refer to section 15.4.5, ?spi clock formats ? for more details. 0 first edge on spsck occurs at the middle of the first cycle of a data transfer 1 first edge on spsck occurs at the start of the first cycle of a data transfer 1 ssoe slave select output enable ? this bit is used in combination with the mode fault enable (modfen) bit in spixc2 and the master/slave (mstr) control bit to determine the function of the ss pin as shown in table 15-2 . 0 lsbfe lsb first (shifter direction) ? this bit does not affect the position of the msb and lsb in the data register. reads and writes of the data register always have the msb in bit 7 (or bit 15 in 16-bit mode). 0 spi serial data transfers start with most significant bit 1 spi serial data transfers start with least significant bit table 15-2. ss pin function modfen ssoe master mode slave mode 0 0 general-purpose i/o (not spi) slave select input 0 1 general-purpose i/o (not spi) slave select input 10s s input for mode fault slave select input 1 1 automatic ss output slave select input
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 247 76543210 r spmie spimode 0 modfen bidiroe 0 spiswai spc0 w r e s e t00000000 = unimplemented or reserved figure 15-6. spi control register 2 (spixc2) table 15-3. spixc2 register field descriptions field description 7 spmie spi match interrupt enable ? this is the interrupt enable for the spi receive data buffer hardware match (spmf) function. 0 interrupts from spmf inhibited (use polling). 1 when spmf = 1, requests a hardware interrupt. 6 spimode spi 8- or 16-bit mode ? this bit allows the user to select either an 8-bit or 16-bit spi data transmission length. in master mode, a change of this bit will abort a transmis sion in progress, force the spi system into idle state, and reset all status bits in the spixs register. refer to section section 15.4.4, ?data transmission length ,? for details. 0 8-bit spi shift register, match register, and buffers. 1 16-bit spi shift register, match register, and buffers. 4 modfen master mode-fault function enable ? when the spi is configured for sl ave mode, this bit has no meaning or effect. (the ss pin is the slave select input.) in mast er mode, this bit determines how the ss pin is used (refer to ta b l e 1 5 - 2 for details) 0 mode fault function disabled, master ss pin reverts to general-purpose i/o not controlled by spi 1 mode fault function enabled, master ss pin acts as the mode fault input or the slave select output 3 bidiroe bidirectional mode output enable ? when bidirectional mode is enabled by spi pin control 0 (spc0) = 1, bidiroe determines whether the spi data output driver is enabled to the single bidirectional spi i/o pin. depending on whether the spi is configured as a master or a slave, it uses either the mosi (momi) or miso (siso) pin, respectively, as the single spi data i/ o pin. when spc0 = 0, bidiroe has no meaning or effect. 0 output driver disabled so spi data i/o pin acts as an input 1 spi i/o pin enabled as an output 1 spiswai spi stop in wait mode ? this bit is used for power conservation while in wait. 0 spi clocks continue to operate in wait mode 1 spi clocks stop when the mcu enters wait mode 0 spc0 spi pin control 0 ? this bit enables bidirectional pin configurations as shown in ta bl e 1 5 - 4 . 0 spi uses separate pins for data input and data output. 1 spi configured for single-wire bidirectional operation.
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 248 freescale semiconductor 15.3.3 spi baud rate register (spixbr) this register is used to set the prescaler and bit rate divisor for an spi master. this register may be read or written at any time. table 15-4. bidirectional pin configurations pin mode spc0 bidiroe miso mosi master mode of operation normal 0 x master in master out bidirectional 1 0 miso not used by spi master in 1 master i/o slave mode of operation normal 0 x slave out slave in bidirectional 1 0 slave in mosi not used by spi 1s l a v e i / o 76543210 r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w r e s e t00000000 = unimplemented or reserved figure 15-7. spi baud rate register (spixbr) table 15-5. spixbr register field descriptions field description 6:4 sppr[2:0] spi baud rate prescale divisor ? this 3-bit field selects one of eight divisors for the spi baud rate prescaler as shown in ta b l e 1 5 - 6 . the input to this prescaler is the bus rate clock (busclk). the output of this prescaler drives the input of the spi baud rate divider (see figure 15-15 ). see section 15.4.6, ?spi baud rate generation ,? for details. 2:0 spr[2:0] spi baud rate divisor ? this 3-bit field selects one of eight diviso rs for the spi baud rate divider as shown in ta b l e 1 5 - 7 . the input to this divider comes fr om the spi baud rate prescaler (see figure 15-15 ). see section 15.4.6, ?spi baud rate generation ,? for details.
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 249 15.3.4 spi status register (spixs) this register has four read-only st atus bits. bits 3 through 0 are not implemented and always read 0. writes have no meaning or effect. table 15-6. spi baud rate prescaler divisor sppr2:sppr1:sppr0 prescaler divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 table 15-7. spi baud rate divisor spr2:spr1:spr0 rate divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 76543210 r sprf spmf sptef modf 0 0 0 0 w r e s e t00100000 = unimplemented or reserved figure 15-8. spi status register (spixs)
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 250 freescale semiconductor 15.3.5 spi data regist ers (spixdh:spixdl) the spi data registers (spixdh:spixdl) are both the input and output re gister for spi data. a write to these registers writes to the transmit data buf fer, allowing data to be queued and transmitted. table 15-8. spixs register field descriptions field description 7 sprf spi read buffer full flag ? sprf is set at the completion of an spi transfer to indicate that received data may be read from the spi data register (spixdh:spixdl). sprf is cleared by reading sprf while it is set, then reading the spi data register. 0 no data available in the receive data buffer. 1 data available in the receive data buffer. 6 spmf spi match flag ? spmf is set after sprf = 1 when the value in the receive data buffer matches the value in spimh:spiml. to clear the fl ag, read spmf when it is set, then write a 1 to it. 0 value in the receive data buffer does not match the value in spixmh:spixml registers. 1 value in the receive data buffer matches the value in spixmh:spixml registers. 5 sptef spi transmit buffer empty flag ? this bit is set when the transmit data bu ffer is empty. it is cleared by reading spixs with sptef set, followed by writing a data value to the transmit buffer at spixdh:spixdl. spixs must be read with sptef = 1 before writing data to spixdh:spixd l or the spixdh:spixdl wr ite will be ignored. sptef is automatically set when all dat a from the transmit buffer transfers into t he transmit shift register. for an idle spi, data written to spixdh:spixdl is transferred to the shif ter almost immediately so sptef is set within two bus cycles allowing a second data to be queued into the transmit buffer. after completion of the transfer of the data in the shift register, the queued data fr om the transmit buffer will automatically move to the shifter and sptef will be set to indicate there is room for new data in the transmit buffer. if no new data is waiting in the transmit buffer, sptef simply remains set and no data moves from the buffer to the shifter. 0 spi transmit buffer not empty 1 spi transmit buffer empty 4 modf master mode fault flag ? modf is set if the spi is configured as a master and the slave select input goes low, indicating some other spi device is also configured as a master. the ss pin acts as a mode fault error input only when mstr = 1, modfen = 1, and ssoe = 0; otherwise, modf will never be set. modf is cleared by reading modf while it is 1, then writing to spi control register 1 (spixc1). 0 no mode fault error 1 mode fault error detected 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset00000000 figure 15-9. spi data register high (spixdh) 76543210 r bit 7654321bit 0 w reset00000000 figure 15-10. spi data register low (spixdl)
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 251 when the spi is configured as a ma ster, data queued in the transmit da ta buffer is transmitted immediately after the previous tran smission has completed. the spi transmit buffer empt y flag (sptef) in the spixs register in dicates when the transmit data buffer is ready to accept new data. spixs must be read when sptef is set before writing to the spi data registers, or the write will be ignored. data may be read from spixdh:spixdl any time after sprf is set and be fore another transfer is finished. failure to read the data out of th e receive data buffer before a new tr ansfer ends causes a receive overrun condition and the data from the new transfer is lost. in 8-bit mode, only spixdl is available. reads of spi xdh will return all 0s. writes to spixdh will be ignored. in 16-bit mode, reading either byte (spixdh or spixdl) latches the c ontents of both byt es into a buffer where they remain latched until the other byte is read. writing to eith er byte (spixdh or spixdl) latches the value into a buffer. when both byt es have been written, they are tran sferred as a cohe rent 16-bit value into the transmit data buffer. 15.3.6 spi match regist ers (spixmh:spixml) these read/write registers contain the hardware compare value, wh ich sets the spi match flag (spmf) when the value received in the spi receive data buffer equals the va lue in the spixmh:spixml registers. in 8-bit mode, only spixml is availa ble. reads of spixmh will return all 0s. writes to spixmh will be ignored. in 16-bit mode, reading either byte (spixmh or spixml) latches the cont ents of both bytes into a buffer where they remain latched until the other byte is rea d. writing to either byte ( spixmh or spixml) latches the value into a buffer. when both bytes have been wr itten, they are transferred as a coherent value into the spi match registers. 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset00000000 figure 15-11. spi match register high (spixmh) 76543210 r bit 7654321bit 0 w reset00000000 figure 15-12. spi match register low (spixml)
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 252 freescale semiconductor 15.4 functional description 15.4.1 general the spi system is enabled by setting the spi enable (spe) bit in spi control register 1. while the spe bit is set, the four associated spi port pins are dedicated to the spi function as: ? slave select (ss ) ? serial clock (spsck) ? master out/slave in (mosi) ? master in/slave out (miso) an spi transfer is initiated in the master spi devi ce by reading the spi status register (spixs) when sptef = 1 and then writing data to the transmit data buffer (write to spixdh:spixdl). when a transfer is complete, received data is moved into the receive data buffer. the spixdh:s pixdl registers act as the spi receive data buffer for reads and as the spi transmit data buffer for writes. the clock phase control bit (cpha) and a clock polarity control bit (cpol) in the spi control register 1 (spixc1) select one of four possi ble clock formats to be used by th e spi system. the cpol bit simply selects a non-inverted or inverted clock. the cpha bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered spsck edges or on even numbered spsck edges. the spi can be configured to operate as a master or as a slave. when th e mstr bit in spi control register 1 is set, master mode is selected, when th e mstr bit is clear, slave mode is selected. 15.4.2 master mode the spi operates in master mode when the mstr b it is set. only a master spi module can initiate transmissions. a transmission begins by reading the spixs register while sptef = 1 and writing to the master spi data registers. if the shif t register is empty, th e byte immediately transfers to the shift register. the data begins shifting out on the mosi pin under the control of the serial clock. ? spsck the spr2, spr1, and spr0 baud rate selection bits in conjunction with th e sppr2, sppr1, and sppr0 baud rate preselection bits in the spi baud rate register control th e baud rate generator and determine the speed of the transmission. the spsc k pin is the spi clock output. th rough the spsck pin, the baud rate generator of the master controls the shift register of the slave peripheral. ? mosi, miso pin in master mode, the function of the serial data output pin (mosi) a nd the serial data i nput pin (miso) is determined by the spc0 an d bidiroe control bits. ?ss pin if modfen and ssoe bit are set, the ss pin is configured as slave select output. the ss output becomes low during each transmission and is high when the spi is in idle state. if modfen is set and ssoe is cleared, the ss pin is configured as input for detecting mode fault error. if the ss input becomes low this indicates a mode fault error wher e another master tries to drive the mosi
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 253 and spsck lines. in this case, th e spi immediately switches to slav e mode, by clearing the mstr bit and also disables the slave output buffer miso (or siso in bidirectional m ode). so the result is that all outputs are disabled and spsck, mo si and miso are inputs. if a transmission is in prog ress when the mode fault occurs, the transmission is aborted a nd the spi is forced into idle state. this mode fault error also sets the mode fault (modf) flag in the spi st atus register (spixs). if the spi interrupt enable bit (spie) is set when the modf flag gets set, then an spi interrupt sequence is also requested. when a write to the spi data register in the master occurs, there is a half spsck-cycle delay. after the delay, spsck is started within the master. the rest of the transfer operation differs sl ightly, depending on the clock format specif ied by the spi clock phase bit, cpha , in spi control register 1 (see section 15.4.5, ?spi clock formats .?) note a change of the bits cpol, cpha, ssoe, lsbfe, modfen, spc0, bidiroe with spc0 set, spimode, sppr2?sppr0 and spr2?spr0 in master mode will abort a transmission in progress and force the spi into idle state. the remote slave cannot detect th is, therefore the master has to ensure that the remote slave is set back to idle state. 15.4.3 slave mode the spi operates in slave mode when the ms tr bit in spi control register1 is clear. ? spsck in slave mode, spsck is the spi clock input from the master. ? miso, mosi pin in slave mode, the function of the serial data output pin (miso) and serial data input pin (mosi) is determined by the spc0 bit and bidiro e bit in spi control register 2. ?ss pin the ss pin is the slave select input. before a data transmission occurs, the ss pin of the slave spi must be low. ss must remain low until the tr ansmission is complete. if ss goes high, the spi is forced into idle state. the ss input also controls the se rial data out put pin, if ss is high (not selected), the serial data output pin is high impedance, and, if ss is low the first bit in the spi data regi ster is driven out of the serial data output pin. also, if the slave is not selected (ss is high), then the spsck input is ignored and no internal shifting of the spi shift register takes place. although the spi is capable of duplex operation, some spi peripherals are capable of only receiving spi data in a slave mode. for these simpler devices, there is no serial data out pin.
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 254 freescale semiconductor note when peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave?s serial data output line. as long as no more than one slave devi ce drives the system slave?s serial data output line, it is possible for several slaves to receive the same transmission from a mast er, although the master wo uld not receive return information from all of the receiving slaves. if the cpha bit in spi control re gister 1 is clear, odd numbered edge s on the spsck input cause the data at the serial data input pin to be latched. even numbered e dges cause the value previ ously latched from the serial data input pin to shift in to the lsb or msb of the spi shif t register, depending on the lsbfe bit. if the cpha bit is set, ev en numbered edges on the spsc k input cause the data at the serial data input pin to be latched. odd numbered edges caus e the value previously latched from the serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. when cpha is set, the first edge is used to get the first data bit onto the serial data output pin. when cpha is clear and the ss input is low (slave selected), the first bit of the spi data is driven out of the serial data output pin. after the eighth (spimode = 0) or sixteenth (spimode = 1) shif t, the transfer is considered complete and the received data is transferred into the spi data registers. to indi cate transfer is complete, the sprf flag in the spi status register is set. note a change of the bits cpol, cpha, ssoe, lsbfe, modfen, spc0 and bidiroe with spc0 set and spimode in slave mode will corrupt a transmission in progress and has to be avoided. 15.4.4 data transmission length the spi can support data lengths of 8 or 16 bits. th e length can be configured with the spimode bit in the spixc2 register. in 8-bit mode (spimode = 0), the spi data register is comprise d of one byte: spixdl. the spi match register is also comprised of only one byte: sp ixml. reads of spixdh and spixmh will return zero. writes to spixdh and sp ixmh will be ignored. in 16-bit mode (spimode = 1), th e spi data register is comprise d of two bytes: spixdh and spixdl. reading either byte (spixdh or spixdl) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. writing to either byte (spixdh or spixdl) latches the value into a buffer. when both bytes have been written, they are transferred as a coherent 16-bit value into the transmit data buffer. in 16-bit mode, the spi match regi ster is also comprised of two bytes: spixmh and spixml. reading either byte (spixmh or spixml) latche s the contents of both bytes into a buffer where they remain latched until the other byte is read. writing to either byte (spixmh or spixml) latches the value into a buffer. when both bytes have been written, they are transferred as a coherent 16-bit valu e into the transmit data buffer.
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 255 any switching between 8- and 16-bit data transmission length (controll ed by spimode bit) in master mode will abort a transmission in progr ess, force the spi system into idle state, and reset all status bits in the spixs register. to initiate a tr ansfer after writing to spimode, the spixs register must be read with sptef = 1, and data must be writ ten to spixdh:spixdl in 16-bit mode (spimode = 1) or spixdl in 8-bit mode (spimode = 0). in slave mode, user software must write to spim ode only once to prevent corrupting a transmission in progress. note data can be lost if the data length is not the same for both master and slave devices. 15.4.5 spi clock formats to accommodate a wide variety of synchronous serial peripherals from differen t manufacturers, the spi system has a clock polarity (cpol) bi t and a clock phase (cpha) control bit to select one of four clock formats for data transfers. cpol se lectively inserts an inverter in series with the clock. cpha chooses between two different clock phase rela tionships between the clock and data. figure 15-13 shows the clock formats when spimode = 0 (8-bit mode) and cpha = 1. at the top of the figure, the eight bit times are shown for reference wi th bit 1 starting at the first spsck edge and bit 8 ending one-half spsck cycle after the sixteenth spsck edge. the msb first and lsb first lines show the order of spi data bits depending on the setting in lsbfe. both variations of spsck polarity are shown, but only one of these waveforms applies for a speci fic transfer, depending on the value in cpol. the sample in waveform applies to the mosi input of a slave or the miso input of a master. the mosi waveform applies to the mosi output pin from a master and the miso waveform applies to the miso output from a slave. the ss out waveform applies to the slave select output from a master (provided modfen and ssoe = 1). the master ss output goes to active low one-half spsck cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. the ss in waveform applies to the slave select input of a slave.
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 256 freescale semiconductor figure 15-13. spi clock formats (cpha = 1) when cpha = 1, the slave begins to drive its miso output when ss goes to active low, but the data is not defined until the first spsck edge. the first spsck edge shifts the first bit of data from the shifter onto the mosi output of the master and the miso output of the slave. the next spsck edge causes both the master and the slave to sample the data bit values on their miso and mosi input s, respectively. at the third spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the mosi and miso outputs of the master and slave, respectively. when cpha = 1, the slave?s ss input is not required to go to its inactive high level between transfers. figure 15-14 shows the clock formats when spimode = 0 and cpha = 0. at the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (ss in goes low), and bit 8 ends at the last spsck edge. the ms b first and lsb first lines show th e order of spi data bits depending on the setting in lsbfe. both vari ations of spsck polarit y are shown, but only one of these waveforms applies for a specific transfer, de pending on the value in cpol. the sa mple in waveform applies to the mosi input of a slave or the mi so input of a master. the mosi waveform applies to the mosi output pin from a master and the miso waveform applies to the miso output from a slave. the ss out waveform applies to the slave sele ct output from a master (provided modfen and ssoe = 1). the master ss output goes to active low at the start of the first bit time of the transfer and goes back high one-half bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 257 spsck cycle after the end of the eight h bit time of th e transfer. the ss in waveform applies to the slave select input of a slave. figure 15-14. spi clock formats (cpha = 0) when cpha = 0, the slave begins to drive its miso output with the first data bit value (msb or lsb depending on lsbfe) when ss goes to active low. the first spsck edge causes both the master and the slave to sample the data bit valu es on their miso and mosi inputs, respectively. at the second spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was ju st sampled and shifts the second data bit value out the other end of the shifte r to the mosi and miso outputs of the master and slave, respectively. when cpha = 0, the slave?s ss input must go to its in active high level between transfers. 15.4.6 spi baud rate generation as shown in figure 15-15 , the clock source for the spi baud rate generator is the bus clock. the three prescale bits (sppr2:sppr1:sppr0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. the three rate select bits (spr2:spr1:spr0) di vide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal spi master mode bit-rate clock. the baud rate generator is activated only when the spi is in the master mode and a serial transfer is taking place. in the other cases, the divider is disabled to decrease i dd current. bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 258 freescale semiconductor the baud rate divisor equation is as follows: the baud rate can be calculated with the following equation: figure 15-15. spi baud rate generation 15.4.7 special features 15.4.7.1 ss output the ss output feature automa tically drives the ss pin low during transmission to select external devices and drives it high duri ng idle to deselect external devices. when ss output is selected, the ss output pin is connected to the ss input pin of the external device. the ss output is available only in ma ster mode during normal spi ope ration by asserting the ssoe and modfen bits as shown in table 15-2 . the mode fault feature is disabled while ss output is enabled. note care must be taken when using the ss output feature in a multi-master system since the mode fault feature is not available for detecting system errors between masters. 15.4.7.2 bidirectional mo de (momi or siso) the bidirectional mode is selected when the spc 0 bit is set in spi control register 2 (see table 15-9 .) in this mode, the spi uses only one serial data pin for the interface with external device(s). the mstr bit decides which pin to use. the mosi pin becomes the serial data i/o (m omi) pin for the master mode, and the miso pin becomes serial data i/o (siso) pin for the slave mode. the miso pin in master mode and mosi pin in slave mode are not used by the spi. baudratedivisor sppr 1 + () 2 ? spr 1 + () = baud rate busclock baudratedivisor ? = divide by 2, 4, 8, 16, 32, 64, 128, or 256 divide by 1, 2, 3, 4, 5, 6, 7, or 8 prescaler baud rate divider sppr2:sppr1:sppr0 spr2:spr1:spr0 bus clock master spi bit rate
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 259 the direction of each serial i/o pin depends on the bidiroe bit. if th e pin is configured as an output, serial data from the shift re gister is driven out on the pin. the same pi n is also the serial input to the shift register. the spsck is output for the master m ode and input for the slave mode. the ss is the input or output for the master mode, a nd it is always the input for the slave mode. the bidirectional mode does not affect spsck and ss functions. note in bidirectional master mo de, with mode fault enab led, both data pins miso and mosi can be occupied by the spi, though mosi is normally used for transmissions in bidirectional mode and miso is not used by the spi. if a mode fault occurs, the spi is automatical ly switched to slave mode, in this case miso becomes occupied by the spi and mosi is not used. this has to be considered, if the miso pi n is used for another purpose. 15.4.8 error conditions the spi has one error condition: ? mode fault error 15.4.8.1 mode fault error if the ss input becomes low while the spi is configured as a mast er, it indicates a system error where more than one master may be trying to drive the mosi and spsck lines s imultaneously. this condition is not permitted in normal operation, and the modf bit in the spi status register is set automatically provided the modfen bit is set. table 15-9. normal mode and bidirectional mode when spe = 1 master mode mstr = 1 slave mode mstr = 0 normal mode spc0 = 0 bidirectional mode spc0 = 1 spi mosi miso serial out serial in spi mosi miso serial in serial out spi momi serial out serial in bidiroe spi siso serial in serial out . bidiroe
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 260 freescale semiconductor in the special case where the spi is in master mode and modfen bit is cleared, the ss pin is not used by the spi. in this special case, the mode fault error function is inhibited and modf re mains cleared. in case the spi system is configured as a slave, the ss pin is a dedicated input pin. mode fault error doesn?t occur in slave mode. if a mode fault error occurs the spi is switched to slave mode, with the exception that the slave output buffer is disabled. so spsck, miso and mosi pins are forced to be high impe dance inputs to avoid any possibility of conflict w ith another output driver. a transmission in progress is aborted and the spi is forced into idle state. if the mode fault error occurs in th e bidirectional mode for a spi system configured in master mode, output enable of the momi (mosi in bidirec tional mode) is cleared if it was se t. no mode fault error occurs in the bidirectional mode for the spi system configured in slave mode. the mode fault flag is cleared automatically by a read of the spi status register (with modf set) followed by a write to spi control register 1. if the mode fault flag is cleare d, the spi becomes a normal master or slave again. 15.4.9 low power mode options 15.4.9.1 spi in run mode in run mode with the spi system enab le (spe) bit in the spi control regist er clear, the spi system is in a low-power, disabled state. spi regi sters can still be accesse d, but clocks to the core of this module are disabled. 15.4.9.2 spi in wait mode spi operation in wait mode depends upon the state of the spiswai bit in spi control register 2. ? if spiswai is clear, the spi operates normally when the cpu is in wait mode ? if spiswai is set, spi clock generation ceases and the spi module enters a power conservation state when the cpu is in wait mode. ? if spiswai is set and the spi is configured for master, any transmis sion and reception in progress stops at wait mode entry. the transm ission and reception resumes when the spi exits wait mode. ? if spiswai is set and the spi is configured as a slave, any transmission and reception in progress continues if the spsck c ontinues to be driven from th e master. this keeps the slave synchronized to the master and the spsck. if the master transmits data while the slave is in wait mode, the slave will continue to send out data consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its spixdh:spixdl to the master, it will c ontinue to send the same byte. otherwise, if the slave is currently sending th e last data received byte from th e master, it will continue to send each previously receive data from the master byte).
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 261 note care must be taken when expecting data from a mast er while the slave is in wait or stop3 mode. even though the shift register will cont inue to operate, the rest of the spi is shut down (i.e. a sprf interrupt will not be generated until exiting stop or wait mode). also, th e data from the shift register will not be copied into the spixdh:spixdl registers until after the slave spi has exited wait or stop mode. a sprf flag and spixdh:spixdl copy is only generated if wait mode is entered or exited during a tranmission. if the slave enters wait mode in idle mode and ex its wait mode in idle mode, neither a sprf nor a spixdh:spixdl copy will occur. 15.4.9.3 spi in stop mode stop3 mode is dependent on the spi system. upon entry to stop3 mode, the spi modu le clock is disabled (held high or low). if the spi is in master mode and exchanging data wh en the cpu enters stop mode, the transmission is frozen until the cpu exits stop mode. after stop, data to and from the external spi is exchanged correctly. in slave mode, the spi will stay synchronized with the master. the stop mode is not dependent on the spiswai bit. in all other stop modes, the spi modu le is completely disabled. after stop, all registers are reset to their default values, and the spi m odule must be re-initialized. 15.4.9.4 reset the reset values of registers and signals are described in section 15.3, ?register definition .? which details the registers and their bit-fields. ? if a data transmission occurs in slave mode after reset without a write to spixdh:spixdl, it will transmit garbage, or the data last re ceived from the master before the reset. ? reading from the spixdh:spixdl after reset will always read zeros. 15.4.9.5 interrupts the spi only originates interrupt re quests when the spi is enabled (spe bit in spixc1 set). the following is a description of how the spi makes a request and how the mcu must acknowledge that request. the interrupt vector offset and interr upt priority are chip dependent. 15.4.10 spi interrupts there are four flag bits, th ree interrupt mask bits, and one interrupt vector associated with the spi system. the spi interrupt enable mask (spie) enables interrupt s from the spi receiver full flag (sprf) and mode fault flag (modf). the spi transm it interrupt enable mask (sptie) enables interrupts from the spi transmit buffer empty flag (sptef). the spi match in terrupt enable mask bit (spimie) enables interrupts from the spi match flag (spm f). when one of the flag bits is set, and the associated interrupt mask bit is set, a hardware interrupt re quest is sent to the cpu. if the interrupt mask bits are cleared, software can poll the associated flag bits instead of using interrupts. the spi interrupt service routin e (isr) must check the
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 262 freescale semiconductor flag bits to determine what event caused the interrupt . the service routine must also clear the flag bit(s) before returning from the isr (usual ly near the beginning of the isr). 15.4.10.1 modf modf occurs when the master detects an error on the ss pin. the master spi must be configured for the modf feature (see table 15-2 ). once modf is set, the current transf er is aborted and th e following bit is changed: ? mstr=0, the master bit in spixc1 resets. the modf interrupt is reflected in the status regist er modf flag. clearing the flag will also clear the interrupt. this interrupt will stay active while the modf flag is set. modf has an automatic clearing process which is described in section 15.3.4, ?spi status register (spixs) .? 15.4.10.2 sprf sprf occurs when new data has been received and copied to the spi receive data buffer. in 8-bit mode, sprf is set only after all 8 bits have been shifted out of the shift regist er and into spixdl. in 16-bit mode, sprf is set only after all 16 bits have been shifte d out of the shift regist er and into spixdh:spixdl. once sprf is set, it does not clear until it is servic ed. sprf has an automatic clearing process which is described in section 15.3.4, ?spi status register (spixs) .? in the event that the sprf is not serviced before the end of the next transf er (i.e. sprf remains active throughout another transfer), the latter transfers will be ignored and no new data will be copied in to the spixdh:spixdl. 15.4.10.3 sptef sptef occurs when the spi transmit buffer is ready to acce pt new data. in 8-bit mode, sptef is set only after all 8 bits have been moved fr om spixdl into the shifter. in 16-bi t mode, sptef is set only after all 16 bits have been moved from spixdh:spixdl into the shifter. once sptef is set, it does not clear until it is serviced. sp tef has an automatic cl earing process which is described in section 15.3.4, ?spi status register (spixs) . 15.4.10.4 spmf spmf occurs when the data in the receive data buffer is equal to the data in the spi match register. in 8-bit mode, spmf is set only after bits 8?0 in the receive data buffer are determined to be equivalent to the value in spixml. in 16-bit mode, spmf is set after bits 1 5?0 in the receive data buffe r are determined to be equivalent to the value in spixmh:spixml.
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 263 15.5 initialization/application information 15.5.1 spi module initialization example 15.5.1.1 initialization sequence before the spi module can be used for communication, an init ialization procedure must be carried out, as follows: 1. update control register 1 (spixc1) to enable the spi and to control interrupt enables. this register also sets the spi as master or slave, determines clock phase and polarity, and configures the main spi options. 2. update control register 2 (spixc2) to enable additional spi functions such as the spi match interrupt feature, the master m ode-fault function, and bi directional mode output . 8- or 16-bit mode select and other optional features are controlled here as well. 3. update the baud rate register ( spixbr) to set the prescaler and b it rate divisor for an spi master. 4. update the hardware match regi ster (spixmh:spixml) with the value to be compared to the receive data register for triggering an interr upt if hardware match interrupts are enabled. 5. in the master, read spixs while sptef = 1, an d then write to the transmit data register (spixdh:spixdl) to begin transfer. 15.5.1.2 pseudo?code example in this example, the spi module will be set up fo r master mode with only hardware match interrupts enabled. the spi will run in 16-bit mode at a maximum baud rate of bus clock divided by 2. clock phase and polarity will be set for an active-high spi clock where the fi rst edge on spsck occu rs at the start of the first cycle of a data transfer. spixc1=0x54(%01010100) bit 7 spie = 0 disables receive and mode fault interrupts bit 6 spe = 1 enables the spi system bit 5 sptie = 0 disables spi transmit interrupts bit 4 mstr = 1 sets the spi module as a master spi device bit 3 cpol = 0 configures spi clock as active-high bit 2 cpha = 1 first edge on spsck at start of first data transfer cycle bit 1 ssoe = 0 determines ss pin function when mode fault enabled bit 0 lsbfe = 0 spi serial data transfers start with most significant bit
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 264 freescale semiconductor spixc2 = 0xc0(%11000000) bit 7 spmie = 1 spi hardware match interrupt enabled bit 6 spimode = 1 configures spi for 16-bit mode bit 5 = 0 unimplemented bit 4 modfen = 0 disables mode fault function bit 3 bidiroe = 0 spi data i/o pin acts as input bit 2 = 0 unimplemented bit 1 spiswai = 0 spi clocks operate in wait mode bit 0 spc0 = 0 uses separate pins for data input and output spixbr = 0x00(%00000000) bit 7 = 0 unimplemented bit 6:4 = 000 sets prescale divisor to 1 bit 3 = 0 unimplemented bit 2:0 = 000 sets baud rate divisor to 2 spixs = 0x00(%00000000) bit 7 sprf = 0 flag is set when receive data buffer is full bit 6 spmf = 0 flag is set when spimh/l = receive data buffer bit 5 sptef = 0 flag is set when transmit data buffer is empty bit 4 modf = 0 mode fault flag for master mode bit 3:0 = 0 unimplemented spixmh = 0xxx in 16-bit mode, this register holds bits 8?15 of the hardware match buffer. in 8-bit mode, writes to this register will be ignored. spixml = 0xxx holds bits 0?7 of the hardware match buffer. spixdh = 0xxx in 16-bit mode, this register holds bits 8?15 of the data to be transmitted by the transmit buffer and received by the receive buffer. spixdl = 0xxx holds bits 0?7 of the data to be transmitted by the transmit buffer and received by the receive buffer.
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 265 figure 15-16. initialization flowchart example for spi master device in 16-bit mode initialize spi spixc1 = 0x54 spixc2 = 0xc0 spixbr = 0x00 spixmh = 0xxx reset yes read spmf while set to clear flag, then write a 1 to it continue spmf = 1 ? read spixdh:spixdl sprf = 1 ? write to spixdh:spixdl sptef = 1 ? no no no yes yes yes
serial peripheral interface (s08spi16v1) MC9S08JM16 series data sheet, rev. 2 266 freescale semiconductor
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 267 chapter 16 timer/pulse-width modulator (s08tpmv2) 16.1 introduction the MC9S08JM16 series includes two independent timer/pwm (tpm) modules (up to 6 channels) that support traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (pwm) on each channel. a control bit in each tpm confi gures all channels in that timer to operate as center-aligned pwm functions . in each of these two tp ms, timing functions are ba sed on a separate 16-bit counter with prescaler a nd modulo features to control frequency and range (period between overflows) of the time reference.
chapter 16 timer/pulse-width modulator (s08tpmv2) MC9S08JM16 series data sheet, rev. 2 268 freescale semiconductor pullup figure 16-1. MC9S08JM16 series block diag ram highlighting the tpm blocks and pins ptc1/sda ptc0/scl v ss v dd pta5, pta0 pte0/txd1 pte1/rxd1 ptd1/adp9/acmp? ptd0/adp8/acmp+ ptc5/rxd2 ptc4 ptc3/txd2 ptc2 port a port c port d 7-bit keyboard interrupt module (kbi) iic module (iic) 8-/16-bit serial peripheral interface module (spi16) user flash (in bytes) user ram (in bytes) on-chip ice and debug module (dbg) mc9s08jm60 = 60,912 hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if irq is enabled (irqpe = 1). pulldown is enabled if risi ng edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. pin contains integrated pullup device. 5. when pin functions as kbi (kbipen = 1) an d associated pin is configured to enable the pullup device, kbedgn can be used to rec onfigure the pullup as a pulldown device. ptb5/kbip5/adp5 port b pte5/mosi1 pte4/miso1 pte6/spsck1 pte7/ss1 hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset v ssad v ddad v refh analog-to-digital converter (adc) ptd7 2 ptb4/kbip4/adp4 ptg3/kbip7 ptg2/kbip6 port g 12-channel, 12-bit bkgd/ms ptf6 ptf7 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 mc9s08jm32 = 32,768 v refl ptg4/xtal ptg5/extal irq/tpmclk rxd2 txd2 sda scl 6 kbipx kbipx spsck1 ss1 miso1 mosi1 rxd1 txd1 extal xtal 2 4 usb sie usb endpoint ram full speed usb transceiver usbdp usbdn miso2 ss2 spsck2 mosi2 ptb1/mosi2/adp1 ptb0/miso2/adp0 8-/16-bit serial peripheral interface module (spi2) real-time counter (rtc) ptb3/ss2 /adp3 ptb2/spsck2/adp2 3 2 analog comparator (acmp) system usb 3.3 v voltage regulator v usb33 mc9s08jm60 = 4096 mc9s08jm32 = 2048 acmpo acmp+ acmp? ptd2/kbip2/acmpo v ssosc pte3/tpm1ch1 pte2/tpm1ch0 port e 2-channel timer/pwm module (tpm2) 4-channel timer/pwm module (tpm1) ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 tpmclk tpmclk tpm1ch1 tpm1ch0 tpm1chx tpm2ch1 tpm2ch0
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 269 16.1.1 features the tpm includes these distinctive features: ? one to eight channels: ? each channel may be input capture, output compare, or edge-aligned pwm ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action ? selectable polarity on pwm outputs ? module may be configured for buffered, center-aligned pulse-w idth-modulation (cpwm) on all channels ? timer clock source selectable as prescaled bus cl ock, fixed system clock, or an external clock pin ? prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128 ? fixed system clock source are synchronized to the bus clock by an on-chip synchronization circuit ? external clock pin may be shared with any timer channel pin or a separated input pin ? 16-bit free-running or modulo up/down count operation ? timer system enable ? one interrupt per channel pl us terminal count interrupt 16.1.2 modes of operation in general, tpm channels may be i ndependently configured to operate in input capture, output compare, or edge-aligned pwm modes. a control bit allows the whole tpm (all ch annels) to switch to center-aligned pwm mode. when cent er-aligned pwm mode is selected, input capture, output compare, and edge-aligned pwm functions are not available on any channels of this tpm module. when the microcontroller is in active bdm ba ckground or bdm foreground m ode, the tpm temporarily suspends all counting until the micr ocontroller returns to normal user operating mode. during stop mode, all system clocks, including the main oscillator, are stopped; therefore, the tpm is effectively disabled until clocks resume. during wait mode, the tpm continues to operate normally. provided the tpm does not need to produce a real time reference or provide the interrupt source(s) need ed to wake the mcu from wait mode, the user can save power by disab ling tpm functions before entering wait mode. ? input capture mode when a selected edge event occurs on the associat ed mcu pin, the current va lue of the 16-bit timer counter is captured into the channel value register and an interrupt flag bit is set. rising edges, falling edges, any edge, or no edge (disable cha nnel) may be selected as the active edge which triggers the input capture. ? output compare mode when the value in the timer counter register matc hes the channel value register, an interrupt flag bit is set, and a selected output action is for ced on the associated mcu pin. the output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions).
MC9S08JM16 series data sheet, rev. 2 270 freescale semiconductor ? edge-aligned pwm mode the value of a 16-bit modulo regist er plus 1 sets the period of the pwm output signal. the channel value register sets the duty cy cle of the pwm output signal. the user may also choose the polarity of the pwm output signal. interrupts are available at the end of the period and at the duty-cycle transition point. this type of pwm signal is calle d edge-aligned because th e leading edges of all pwm signals are aligned with the beginning of the period, which is th e same for all channels within a tpm. ? center-aligned pwm mode twice the value of a 16-bit modulo register sets the period of the pwm output, and the channel-value register sets th e half-duty-cycle duration. the timer counter counts up until it reaches the modulo value and then counts down unt il it reaches zero. as the count matches the channel value register while counting down, the pwm output becomes active. when the count matches the channel value register while countin g up, the pwm output becomes inactive. this type of pwm signal is called center-aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero. this t ype of pwm is required for types of motors used in small appliances. this is a high-level description onl y. detailed descriptions of opera ting modes are in later sections. 16.1.3 block diagram the tpm uses one input/output (i/o) pin per channel, tpmxchn (timer channel n) where n is the channel number (1-8). the tpm shares its i/o pins with general purpos e i/o port pins (refer to i/o pin descriptions in full-chip specification for th e specific chip implementation). figure 16-2 shows the tpm structure. the central component of the tpm is the 16-bit counter that can operate as a free-running counter or a modulo up/ down counter. the tpm counter (when operating in normal up-counting mode) provides the timing referenc e for the input capture, output compare, and edge-aligned pwm functions. the timer counter mo dulo registers, tpmxmodh:tpmxmodl, control the modulo value of the counter (the values 0x0000 or 0xffff effectivel y make the counter free running). software can read the counter value at any time wi thout affecting the counti ng sequence. any write to either half of the tpmxcnt counter resets th e counter, regardless of the data value written.
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 271 figure 16-2. tpm block diagram prescale and select 16-bit comparator ps2:ps1:ps0 tof toie inter- 16-bit counter rupt logic 16-bit comparator 16-bit latch els0b els0a port channel 0 ch0ie ch0f logic inter- rupt logic cpwms ms0b ms0a counter reset clksb:clksa 31, 2, 4, 8, 16, 32, 64, bus clock fixed system clock external clock sync 16-bit comparator 16-bit latch channel 1 els1b els1a ch1ie ch1f internal bus port logic inter- rupt logic ms1b ms1a 16-bit comparator 16-bit latch channel 7 els7b els7a ch7ie ch7f port logic inter- rupt logic ms7b ms7a up to 8 channels clock source select off, bus, fixed system clock, ext or 3128 tpmxmodh:tpmxmodl tpmxc0vh:tpmxc0vl tpmxc1vh:tpmxc1vl tpmxch0 tpmxch1 tpmxc7vh:tpmxc7vl tpmxch7
MC9S08JM16 series data sheet, rev. 2 272 freescale semiconductor the tpm channels are programmable independently as input capture, output co mpare, or edge-aligned pwm channels. alternately, the tpm can be configur ed to produce cpwm outputs on all channels. when the tpm is configured for cpwms, the counter ope rates as an up/down count er; input capture, output compare, and epwm func tions are not practical. if a channel is configured as input capture, an internal pullup device may be enabled for that channel. the details of how a module interacts w ith pin controls depends upon the ch ip implementation because the i/o pins and associated general purpose i/ o controls are not part of the modul e. refer to the di scussion of the i/o port logic in a full-chip specification. because center-aligned pwms are usually used to drive 3-phase ac-induction motors and brushless dc motors, they are typically used in sets of three or six channels. 16.2 signal description table 16-1 shows the user-accessible signals for the tpm. the number of channels may be varied from one to eight. when an external cloc k is included, it can be shared with the same pin as any tpm channel; however, it could be connected to a separate input pin. refer to the i/o pin descriptions in full-chip specification for the speci fic chip implementation. refer to documentation for the full-chip for details ab out reset states, port connections, and whether there is any pullup device on these pins. tpm channel pins can be associated with general purpose i/ o pins and have passiv e pullup devices which can be enabled with a control bit when the tpm or general purpose i/o controls have configured the associated pin as an input. when no tpm function is enabled to us e a corresponding pin, the pin reverts to being controlled by general purpose i/o controls, including the port-da ta and data-direction registers. immediately after reset, no tpm functions are enabled, so all associated pins revert to general purpose i/o control. 16.2.1 detailed signal descriptions this section describes each user-acce ssible pin signal in detail. although table 16-1 grouped all channel pins together, any tpm pin can be sh ared with the external clock source signal. since i/o pin logic is not part of the tpm, refer to full-ch ip documentation for a specific derivative for more details about the interaction of tpm pin functions a nd general purpose i/o controls incl uding port data, data direction, and pullup controls. table 16-1. signal properties name function extclk 1 1 when preset, this signal can share any channel pin; however depending upon full-chip implementation, this signal could be connected to a separate external pin. external clock source which may be selected to drive the tpm counter. tpmxchn 2 2 n=channel number (1 to 8) i/o pin associated with tpm channel n
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 273 16.2.1.1 extclk ? external clock source control bits in the timer status a nd control register allow the user to select nothing (tim er disable), the bus-rate clock (the normal de fault source), a crystal-related clock, or an external clock as the clock which drives the tpm prescaler and subsequently the 16-bit tpm counter . the external clock source is synchronized in the tpm. th e bus clock clocks the synchronizer; the frequency of the external source must be no more than one-fourth the fre quency of the bus-rate clock, to meet nyquist criteria and allowing for jitter. the external clock signal shares the same pin as a ch annel i/o pin, so the channel pin will not be usable for channel i/o function when selected as the external cl ock source. it is the user?s responsibility to avoid such settings. if this pin is used as an external clock source (clksb:clksa = 1:1), the channel can still be used in output compare mode as a software timer (elsnb:elsna = 0:0). 16.2.1.2 tpmxchn ? tpm channel n i/o pin(s) each tpm channel is associated with an i/o pin on the mcu. the function of this pin depends on the channel configuration. the tpm pins share with general purpose i/o pins, where each pin has a port data register bit, and a data di rection control bit, and the port has optional passive pullups which may be enabled whenever a port pin is acting as an input. the tpm channel does not control th e i/o pin when (elsnb:elsna = 0:0) or when (clksb:clksa = 0:0) so it normally reverts to general purpose i/ o control. when cpwms = 1 (and elsnb:elsna not = 0:0), all channels within the tpm are configured for center-aligned pwm and the tpmxchn pins are all controlled by the tpm system. when cpwms=0, the msnb:msna control bits determine whether the channel is configured for input captur e, output compare, or edge-aligned pwm. when a channel is configured for input capture (cpwms=0, msnb :msna = 0:0 and elsnb:elsna not = 0:0), the tpmxchn pin is forced to act as an e dge-sensitive input to the tpm. elsnb:elsna control bits determine what polarity edge or edges will trigger input-capture events. a synchronizer based on the bus clock is used to synchronize i nput edges to the bus cl ock. this implies the minimum pulse width?that can be reliably detected?on an input capture pin is four bus clock periods (with ideal cloc k pulses as near as two bus clocks can be detected). tpm uses this pi n as an input capture inpu t to override the port data and data direction controls for the same pin. when a channel is configured for output comp are (cpwms=0, msnb:msna = 0:1 and elsnb:elsna not = 0:0), the associated data direction control is overridden, the tp mxchn pin is considered an output controlled by the tpm, and the elsnb:elsna contro l bits determine how the pin is controlled. the remaining three combinations of elsnb:elsna dete rmine whether the tpmxchn pin is toggled, cleared, or set each time the 16-bit channel value register matches the timer counter. when the output compare toggle mode is initially select ed, the previous value on th e pin is driven out until the next output compare event?then the pin is toggled.
MC9S08JM16 series data sheet, rev. 2 274 freescale semiconductor when a channel is configured for edge-aligne d pwm (cpwms=0, msnb=1 and elsnb:elsna not = 0:0), the data direction is overridden, the tpmxchn pin is forced to be an output controlled by the tpm, and elsna controls the polarity of the pwm out put signal on the pin. when elsnb:elsna=1:0, the tpmxchn pin is forced high at the start of each new period (tpmxc nt=0x0000), and the pin is forced low when the channel value register matches the timer counter. when elsna=1, the tpmxchn pin is forced low at the start of each new period (tpm xcnt=0x0000), and the pin is forced high when the channel value register matches the timer counter. figure 16-3. high-true pulse of an edge-aligned pwm figure 16-4. low-true pulse of an edge-aligned pwm chnf bit tof bit 0 ... 1 2 345 6 780 12... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmxchn chnf bit tof bit 0 ... 1 2 345 6 780 12... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmxchn
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 275 when the tpm is configur ed for center-aligned pwm (and elsnb: elsna not = 0:0), th e data direction for all channels in this tpm are overridden, the tpmxchn pins are forc ed to be outputs controlled by the tpm, and the elsna bits control the polarity of each tpmxchn output. if elsnb:elsna=1:0, the corresponding tpmxchn pin is cleared when the timer counter is counting up, and the channel value register matches the timer counter; the tpmxchn pin is set when the timer counter is counting down, and the channel value register matche s the timer counter. if elsna=1, the corresponding tpmxchn pin is set when the timer counter is counting up and the chan nel value register matches the timer counter; the tpmxchn pin is cleared wh en the timer counter is counting down and the cha nnel value register matches the timer counter. figure 16-5. high-true pulse of a center-aligned pwm figure 16-6. low-true pulse of a center-aligned pwm chnf bit tof bit ... 78 765 4 321 012 34 56 78 76 5 ... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmxchn chnf bit tof bit ... 78 765 4 321 012 34 56 78 76 5... tpmxmodh:tpmxmodl = 0x0008 tpmxmodh:tpmxmodl = 0x0005 tpmxcnth:tpmxcntl tpmxchn
MC9S08JM16 series data sheet, rev. 2 276 freescale semiconductor 16.3 register definition this section consists of register descriptions in address order. a typical mcu syst em may contain multiple tpms, and each tpm may have one to eight channels, so register names include placeholder characters to identify which tpm and which channel is being refe renced. for example, tpmxcnsc refers to timer (tpm) x, channel n. tpm1c2sc would be the status and control register for channel 2 of timer 1. 16.3.1 tpm status and control register (tpmxsc) tpmxsc contains the overflow status flag and control bits used to configure the interrupt enable, tpm configuration, clock source, and prescale factor. these controls relate to all channels within this timer module. 76543210 rtof toie cpwms clksb clksa ps2 ps1 ps0 w0 reset00000000 figure 16-7. tpm status and control register (tpmxsc) table 16-2. tpmxsc field descriptions field description 7 tof timer overflow flag. this read/write flag is set when the tpm counter resets to 0x0000 after reaching the modulo value programmed in the tpm counter modulo register s. clear tof by reading the tpm status and control register when tof is set and then writing a logic 0 to tof. if another tpm overflow occurs before the clearing sequence is complete, the sequence is reset so tof would remain set after the clear sequence was completed for the earlier tof. this is done so a tof interrupt request cannot be lost during the clearing sequence for a previous tof. reset clears tof. writing a logic 1 to tof has no effect. 0 tpm counter has not reached modulo value or overflow 1 tpm counter has overflowed 6 toie timer overflow interrupt enable. this read/write bit enables tpm overflow interrupts. if toie is set, an interrupt is generated when tof equals one. reset clears toie. 0 tof interrupts inhibited (use for software polling) 1 tof interrupts enabled 5 cpwms center-aligned pwm select. when present, this read/wri te bit selects cpwm operating mode. by default, the tpm operates in up-counting mode for input capture, out put compare, and edge-aligned pwm functions. setting cpwms reconfigures the tpm to operate in up/down counting mode for cpwm functions. reset clears cpwms. 0 all channels operate as input capture, output compare, or edge-aligned pwm mode as selected by the msnb:msna control bits in each ch annel?s status and control register. 1 all channels operate in center-aligned pwm mode.
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 277 16.3.2 tpm-counter regist ers (tpmxcnth:tpmxcntl) the two read-only tpm counter regist ers contain the high and low bytes of the value in the tpm counter. reading either byte (tpmxcnth or tpmxcntl) latches the contents of both bytes into a buffer where they remain latched until the other half is read. this allows coherent 16-bit reads in either big-endian or little-endian order which makes th is more friendly to various comp iler implementations. the coherency mechanism is automatically restarted by an mcu reset or any write to the time r status/control register (tpmxsc). 4?3 clks[b:a] clock source selects. as shown in table 16-3 , this 2-bit field is used to disabl e the tpm system or select one of three clock sources to drive the counter prescaler. the fixed system clock source is only meaningful in systems with a pll-based or fll-based system cl ock. when there is no pll or fll, the fixed-system clock source is the same as the bus rate clock. the external source is synchronized to the bus clock by tpm module, and the fixed system clock source (when a pll or fll is present) is synchronized to the bus clock by an on-chip synchronization circuit. when a pll or fll is present but not e nabled, the fixed-system clock source is the same as the bus-rate clock. 2?0 ps[2:0] prescale factor select. this 3-bit field selects one of 8 division factors for the tpm clock input as shown in ta b l e 1 6 - 4 . this prescaler is located after any clock source syn chronization or clock source selection so it affects the clock source selected to drive the tpm system. the new prescale factor will affect the clock source on the next system clock cycle after the new value is updated into the register bits. table 16-3. tpm-clock-source selection clksb:clksa tpm clock so urce to prescaler input 00 no clock selected (tpm counter disable) 01 bus rate clock 10 fixed system clock 11 external source table 16-4. prescale factor selection ps2:ps1:ps0 tpm clock source divided-by 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 table 16-2. tpmxsc field descriptions (continued) field description
MC9S08JM16 series data sheet, rev. 2 278 freescale semiconductor reset clears the tpm count er registers. writing a ny value to tpmxcnth or tpmxcntl also clears the tpm counter (tpmxcnth:tpmxcntl) and resets the coherency mechanism, regardless of the data involved in the write. when bdm is active, the time r counter is frozen (this is the value that will be re ad by user); the coherency mechanism is frozen such that the buffer latches rema in in the state they were in when the bdm became active, even if one or both counter halves are read whil e bdm is active. this assu res that if the user was in the middle of reading a 16- bit register when bdm beca me active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. in bdm mode, writing any value to tpmxsc, tpmx cnth or tpmxcntl registers resets the read coherency mechanism of the tpmxcn th:l registers, regardless of the data involved in the write. 16.3.3 tpm counter modulo re gisters (tpmxmodh:tpmxmodl) the read/write tpm modulo registers contain the modulo value for the tpm counter. after the tpm counter reaches the modulo value, the tpm counter resumes counting from 0x0000 at the next clock, and the overflow flag (tof) becomes set. writing to tpmxmodh or tpmxmodl i nhibits the tof bit and overflow interrupts until the other byte is written. reset sets the tp m counter modulo registers to 0x0000 which results in a free running timer counter (modulo disabled). writing to either byte (tpmxmodh or tpmxmodl) latches the value into a buffer and the registers are updated with the value of their write buffer acco rding to the value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), then the registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), then the registers are updated after both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmo dl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter, the update is made when the tpm counter changes from 0xfffe to 0xffff the latching mechanism may be manually reset by writing to the tp mxsc address (w hether bdm is active or not). 76543210 r bit 15 14 13 12 11 10 9 bit 8 w any write to tpmxcnth clears the 16-bit counter r e s e t00000000 figure 16-8. tpm counter register high (tpmxcnth) 76543210 rb i t 7654321b i t 0 w any write to tpmxcntl clears the 16-bit counter r e s e t00000000 figure 16-9. tpm counter register low (tpmxcntl)
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 279 when bdm is active, the coherency mechanism is frozen (unless reset by writing to tpmxsc register) such that the buffer latches remain in the state they were in when the bdm becam e active, even if one or both halves of the modulo register are written while bdm is active. a ny write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while bdm is active. reset the tpm counter before writin g to the tpm modulo registers to a void confusion about when the first counter overflow will occur. 16.3.4 tpm channel n status an d control register (tpmxcnsc) tpmxcnsc contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset00000000 figure 16-10. tpm counter modulo register high (tpmxmodh) 76543210 r bit 7654321bit 0 w reset00000000 figure 16-11. tpm counter modulo register low (tpmxmodl) 76543210 rchnf chnie msnb msna elsnb elsna 00 w0 r e s e t00000000 = unimplemented or reserved figure 16-12. tpm channel n status and control register (tpmxcnsc)
MC9S08JM16 series data sheet, rev. 2 280 freescale semiconductor table 16-5. tpmxcnsc field descriptions field description 7 chnf channel n flag. when channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. when channel n is an output com pare or edge-aligned/center-aligned pwm channel, chnf is set when the value in the tpm counter registers matches the value in the tpm channel n value registers. when channel n is an edge-aligned/center-aligned pwm channel and the duty cycle is set to 0% or 100%, chnf will not be set even when the value in the tpm counter registers ma tches the value in the tpm channel n value registers. a corresponding interrupt is requested when chnf is set and interrupts are enabled (chnie = 1). clear chnf by reading tpmxcnsc while chnf is set and then writing a logic 0 to chnf. if another interrupt request occurs before the clearing sequence is complete, the sequence is reset so chnf remains set after the clear sequence completed for the earlier chnf. this is done so a chnf interr upt request cannot be lost due to clearing a previous chnf. reset clears the chnf bit. writing a logic 1 to chnf has no effect. 0 no input capture or output compare event occurred on channel n 1 input capture or output compare event on channel n 6 chnie channel n interrupt enable. this read/write bit enables interrupts from channel n. reset clears chnie. 0 channel n interrupt requests disabled (use for software polling) 1 channel n interrupt requests enabled 5 msnb mode select b for tpm channel n. when cpwms=0, ms nb=1 configures tpm channel n for edge-aligned pwm mode. refer to the summary of channel mode and setup controls in table 16-6 . 4 msna mode select a for tpm channel n. when cpwms=0 and msnb=0, msna configures tpm channel n for input-capture mode or output compare mode. refer to ta bl e 1 6 - 6 for a summary of channel mode and setup controls. note: if the associated port pin is not stable for at least two bus cl ock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. 3?2 elsnb elsna edge/level select bits. depending upon the operating mo de for the timer channel as set by cpwms:msnb:msna and shown in table 16-6 , these bits select the polarity of the input e dge that triggers an input capture event, select the level that will be driven in response to an output co mpare match, or select the polarity of the pwm output. setting elsnb:elsna to 0:0 configures the related timer pin as a general purpose i/o pin not related to any timer functions. this function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general purpose i/o pin when the associated timer channel is set up as a software timer that does not require the use of a pin. table 16-6. mode, edge, and level selection cpwms msnb:msna elsnb:el sna mode configuration x xx 00 pin not used for tpm - revert to general purpose i/o or other peripheral control
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 281 16.3.5 tpm channel value registers (tpmxcnvh:tpmxcnvl) these read/write register s contain the captured tpm counter value of the input capture function or the output compare value for the output compare or pw m functions. the channel registers are cleared by reset. in input capture mode, reading eith er byte (tpmxcnvh or tpmxcnvl) la tches the contents of both bytes into a buffer where they remain latched until the othe r half is read. this latching mechanism also resets 0 00 01 input capture capture on rising edge only 10 capture on falling edge only 11 capture on rising or falling edge 01 01 output compare toggle output on compare 10 clear output on compare 11 set output on compare 1x 10 edge-aligned pwm high-true pulses (clear output on compare) x1 low-true pulses (set output on compare) 1 xx 10 center-aligned pwm high-true pulses (clear output on compare-up) x1 low-true pulses (set output on compare-up) 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset00000000 figure 16-13. tpm channel value register high (tpmxcnvh) 76543210 r bit 7654321bit 0 w reset00000000 figure 16-14. tpm channel value register low (tpmxcnvl) table 16-6. mode, edge, and level selection cpwms msnb:msna elsnb:el sna mode configuration
MC9S08JM16 series data sheet, rev. 2 282 freescale semiconductor (becomes unlatched) when the tpmxcnsc register is wr itten (whether bdm mode is active or not). any write to the channel registers will be ignored during the input capture mode. when bdm is active, the coherency mechanism is fro zen (unless reset by writi ng to tpmxcnsc register) such that the buffer latches remain in the state they were in when the bdm becam e active, even if one or both halves of the channel register are read while bdm is active. this assures that if the user was in the middle of reading a 16-bit register when bdm became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. the value read from the tpmxcnvh and tpmxcnvl registers in bdm mode is the value of these registers and not the value of their read buffer. in output compare or pwm modes, writing to either byte (tpmxcnvh or tpmxcnvl) latches the value into a buffer. after both bytes are written, they are transferred as a coherent 16-bit value into the timer-channel registers according to the value of clksb:clksa bits and the selected mode, so: ? if (clksb:clksa = 0:0), then the registers are updated when the second byte is written. ? if (clksb:clksa not = 0:0 and in output compare mode) then the registers are updated after the second byte is written and on the next change of the tpm counter (end of the prescaler counting). ? if (clksb:clksa not = 0:0 and in epwm or cpwm modes), then the registers are updated after the both bytes were written, and the tpm count er changes from (tpm xmodh:tpmxmodl - 1) to (tpmxmodh:tpmxmodl). if th e tpm counter is a free-running counter then the update is made when the tpm counter changes from 0xfffe to 0xffff. the latching mechanism may be manually reset by writing to the tpmxcnsc register (whether bdm mode is active or not). this latchi ng mechanism allows cohe rent 16-bit writes in either big-endian or little-endian order which is friendly to various compiler implementations. when bdm is active, the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the bdm became active even if one or both halves of the channel register are written while bdm is active. any write to the channel regist ers bypasses the buffer latche s and directly write to the channel register while bdm is act ive. the values written to the ch annel register while bdm is active are used for pwm & output compare operation once nor mal execution resumes. writes to the channel registers while bdm is acti ve do not interfere with partial comple tion of a coherency sequence. after the coherency mechanism has been fully exercised, the channel registers ar e updated using the buffered values written (while bdm was not active) by the user. 16.4 functional description all tpm functions are associ ated with a central 16-bit counter which allows flexible selection of the clock source and prescale factor. there is also a 16-bit modulo register associated with the main counter. the cpwms control bit chooses be tween center-aligned pwm operation for all channels in the tpm (cpwms=1) or general purpose ti ming functions (cpwms=0) where each channel can independently be configured to operate in input capture, output co mpare, or edge-aligned pwm mode. the cpwms control bit is located in the main tpm status and control regi ster because it affects all channels within the tpm and influences the wa y the main counter operates. (in cpwm m ode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.)
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 283 the following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned pwm, and center-aligned pwm). because details of pin operation and interrupt activity depend upon the opera ting mode, these topics will be covered in the associated mode explanation sections. 16.4.1 counter all timer functions are based on the main 16-bit counter (tpmxcnth:tpmxcntl). this section discusses selection of the clock source, end-of-count overflow, up- counting vs. up/down counting, and manual counter reset. 16.4.1.1 counter clock source the 2-bit field, clksb:clksa, in the timer status a nd control register (tpmxs c) selects one of three possible clock sources or off (which effectively disabl es the tpm). see table 16-3 . after any mcu reset, clksb:clksa=0:0 so no clock source is selected, and the tpm is in a very low power state. these control bits may be read or writ ten at any time and disabling the timer (writing 00 to the clksb:clksa field) does not affect the values in the counter or other timer registers.
MC9S08JM16 series data sheet, rev. 2 284 freescale semiconductor the bus rate clock is the main system bus cl ock for the mcu. this clock source requires no synchronization because it is the clock that is used for all inte rnal mcu activities including operation of the cpu and buses. in mcus that have no pll and fll or the pll and fll are not engage d, the fixed system clock source is the same as the bus-rate-clock source, and it does not go through a synchronizer. when a pll or fll is present and engaged, a synchronize r is required between the crystal di vided-by two clock source and the timer counter so counter transitions will be properly aligne d to bus-clock transiti ons. a synchronizer will be used at chip level to synchronize the crystal-related source clock to the bus clock. the external clock source may be connected to any tpm ch annel pin. this clock source always has to pass through a synchronizer to assure that counter transitions are properly aligned to bus clock transitions. the bus-rate clock drives the synchronizer; therefore, to meet nyquist criteria even with jitter, the frequency of the external clock source must not be faster than the bus rate divided-by f our. with ideal clocks the external clock can be as fast as bus clock divided by four. when the external clock source shar es the tpm channel pin, this pin s hould not be used for other channel timing functions. for example, it w ould be ambiguous to configure channel 0 for input capture when the tpm channel 0 pin was also being used as the timer external clock source . (it is the user?s responsibility to avoid such settings.) the tpm channel could still be used in output compare mode for software timing functions (pin controls set not to affect the tpm channel pin). 16.4.1.2 counter overflow and modulo reset an interrupt flag and enable are associated wi th the 16-bit main counter. the flag (tof) is a software-accessible indication that the timer counter has overflowed. th e enable signal selects between software polling (toie=0) where no hardware interrupt is generated, or interrupt-driven operation (toie=1) where a static hardware interrupt is generated whenever the tof flag is equal to one. the conditions causing tof to become set depend on whether the tpm is configured for center-aligned pwm (cpwms=1). in the simplest mode, there is no modulus limit and the tpm is not in cpwms=1 mode. in this case, the 16-bit timer counter counts from 0x0000 th rough 0xffff and overflows to 0x0000 on the next counting clock. tof becomes set at the transition fr om 0xffff to 0x0000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to 0x0000. when the tpm is in center-aligned pwm mode (cpwms=1), the tof flag ge ts set as the counter changes direction at the end of the count valu e set in the modulus register (that is, at the transition from the value set in the modulus register to the next lower count value). this corresponds to the end of a pwm period (the 0x0000 count value corresponds to the center of a period). table 16-7. tpm clock source selection clksb:clksa tpm clock source to prescaler input 00 no clock selected (t pm counter disabled) 01 bus rate clock 10 fixed system clock 11 external source
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 285 16.4.1.3 counting modes the main timer counter has two c ounting modes. when center-aligned pwm is selected (cpwms=1), the counter operates in up/down counting mode. otherwise, the counter operates as a simple up counter. as an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. the terminal count is 0xffff or a modulus value in tpmxmodh:tpmxmodl. when center-aligned pwm operation is specified, th e counter counts up from 0x0000 through its terminal count and then down to 0x0000 where it changes back to up count ing. both 0x0000 and th e terminal count value are normal length counts (one tim er clock period long). in this m ode, the timer overflow flag (tof) becomes set at the end of the terminal-count period (a s the count changes to the next lower count value). 16.4.1.4 manual counter reset the main timer counter can be manually reset at any time by writing any value to either half of tpmxcnth or tpmxcntl. resetting the counter in this manner also resets the coherency mechanism in case only half of the counter wa s read before resetting the count. 16.4.2 channel mode selection provided cpwms=0, the msnb and msna control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. choices include input capture, output compare, and edge-aligned pwm. 16.4.2.1 input capture mode with the input-capture function, the tpm can capture the time at which an exte rnal event occurs. when an active edge occurs on the pin of an input-capture channel, the tpm latches the contents of the tpm counter into the channel-value registers (tpmxcnvh: tpmxcnvl). rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. in input capture mode, the tpmxcnvh and tpmxcnvl registers are read only. when either half of the 16-bit capture register is read, the other half is latched into a buffer to support coherent 16-bit accesses in big-endi an or little-endian order. the coherency sequence can be manually reset by writing to the channel st atus/control register (tpmxcnsc). an input capture event sets a flag bit (chnf) wh ich may optionally generate a cpu interrupt request. while in bdm, the input ca pture function works as conf igured by the user. when an external event occurs, the tpm latches the contents of the tpm counter (which is frozen because of the bdm mode) into the channel value registers and sets the flag bit. 16.4.2.2 output compare mode with the output-compare function, the tpm can ge nerate timed pulses with programmable position, polarity, duration, and frequency. when the counter reach es the value in the channel-value registers of an output-compare channel, the tpm can se t, clear, or toggle the channel pin.
MC9S08JM16 series data sheet, rev. 2 286 freescale semiconductor in output compare mode, values are transferred to th e corresponding timer channel registers only after both 8-bit halves of a 16-bit register ha ve been written and according to the value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), th e registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), th e registers are updated at the ne xt change of the tpm counter (end of the prescaler counting) after the second byte is written. the coherency sequence can be manually reset by wr iting to the channel st atus/control register (tpmxcnsc). an output compare event sets a flag bit (chnf) wh ich may optionally generate a cpu-interrupt request. 16.4.2.3 edge-aligned pwm mode this type of pwm output uses the normal up-counti ng mode of the timer c ounter (cpwms=0) and can be used when other channels in the same tpm ar e configured for input cap ture or output compare functions. the period of this pwm signal is dete rmined by the value of the modulus register (tpmxmodh:tpmxmodl) plus 1. the duty cycle is determined by the setting in the timer channel register (tpmxcnvh:tpmxcn vl). the polarity of this pwm signal is determined by the setting in the elsna control bit. 0% and 100% duty cycle cases are possible. the output compare value in the tpm channel registers determines the pulse wi dth (duty cycle) of the pwm signal ( figure 16-15 ). the time between the modulus overflo w and the output compare is the pulse width. if elsna=0, the counter overflow forces the pwm signal high, and the out put compare forces the pwm signal low. if elsna=1, the c ounter overflow forces the pwm si gnal low, and the output compare forces the pwm signal high. figure 16-15. pwm period and pulse width (elsna=0) when the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved by setting the timer-channel regi ster (tpmxcnvh:tpmxcnvl) to a value greater than the modulus setting. this implies that the modulus setting must be less than 0xffff in order to get 100% duty cycle. because the tpm may be used in an 8-bit mcu, the se ttings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to any of the registers tpmxcnvh and tpmxcnvl, actually wr ite to buffer registers. in e dge-aligned pwm mode, values are transferred to the corresponding timer- channel registers according to th e value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), th e registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), th e registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmo dl - 1) to (tpmxmodh:tpmxmodl). if period pulse width overflow overflow overflow output compare output compare output compare tpmxchn
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 287 the tpm counter is a fr ee-running counter then the update is made when the tpm counter changes from 0xfffe to 0xffff. 16.4.2.4 center-aligned pwm mode this type of pwm output uses th e up/down counting mode of the timer counter (cpwms=1). the output compare value in tpmxcnvh:tpmxcnvl determines the pulse width (duty cycle) of the pwm signal while the period is determined by the value in tpmxmodh:tpmxmodl. tpmxmodh:tpmxmodl should be kept in the range of 0x0001 to 0x7fff becaus e values outside this ra nge can produce ambiguous results. elsna will determine the polarity of the cpwm output. pulse width = 2 x (tpmxcnvh:tpmxcnvl) period = 2 x (tpmxmodh:tpmxmodl ); tpmxmodh:tpmxmodl=0x0001-0x7fff if the channel-value register tpmxcnvh:tpmxcnvl is zero or negative (bit 15 set), the duty cycle will be 0%. if tpmxcnvh:tpmxcnvl is a positive value (bit 15 clear) and is greater than the (non-zero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. this implies the usable range of periods set by the modulus register is 0x0001 through 0x7ffe (0x7fff if you do not need to generate 100% duty cycle). this is not a significant limitation. the resu lting period would be much longer than required for normal applications. tpmxmodh:tpmxmodl=0x0000 is a special case that should not be used wi th center-aligned pwm mode. when cpwms=0, this case co rresponds to the counter runni ng free from 0x0000 through 0xffff, but when cpwms=1 the counter needs a valid match to the modulus register so mewhere other than at 0x0000 in order to change directions from up-counting to down-counting. the output compare value in the tpm channel registers (times 2) determines the pulse width (duty cycle) of the cpwm signal ( figure 16-16 ). if elsna=0, a compare occurred while counting up forces the cpwm output signal low and a compare occurred while counting down forc es the output high. the counter counts up until it reaches the modulo se tting in tpmxmodh:tpmxmodl, then counts down until it reaches zero. this sets the period equal to two times tpmxmodh:tpmxmodl. figure 16-16. cpwm period and pulse width (elsna=0) center-aligned pwm outputs typically produce less noise than edge-aligned pwms because fewer i/o pin transitions are lined up at the same system clock edge. this type of pwm is also require d for some types of motor drives. period pulse width count= count= 0 count= output compare (count down) output compare (count up) tpmxchn 2 x tpmxmodh:tpmxmodl 2 x tpmxcnvh:tpmxcnvl tpmxmodh:tpmxmodl tpmxmodh:tpmxmodl
MC9S08JM16 series data sheet, rev. 2 288 freescale semiconductor input capture, output compare, a nd edge-aligned pwm functions do not make sense when the counter is operating in up/down counting mode so th is implies that all act ive channels within a tpm must be used in cpwm mode when cpwms=1. the tpm may be used in an 8-bit mc u. the settings in the timer channe l registers are buffered to ensure coherent 16-bit updates and to a void unexpected pwm pulse widths. wr ites to any of the registers tpmxmodh, tpmxmodl, tpmxcnvh, and tpmxcnvl , actually write to buffer registers. in center-aligned pwm mode, the tpmxcnvh:l registers are updated with the value of their write buffer according to the value of clksb:clksa bits, so: ? if (clksb:clksa = 0:0), th e registers are updated when the second byte is written ? if (clksb:clksa not = 0:0), th e registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmo dl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter, the update is made when the tpm counter changes from 0xfffe to 0xffff. when tpmxcnth:tpmxcntl=tpmxmodh:tpmxmodl, the tpm can optionally generate a tof interrupt (at the end of this count). writing to tpmxsc cancels any values written to tpmxmodh and/or tpmxmodl and resets the coherency mechanism for the modulo re gisters. writing to tpmxcnsc ca ncels any values written to the channel value registers and resets the c oherency mechanism for tpmxcnvh:tpmxcnvl. 16.5 reset overview 16.5.1 general the tpm is reset whenever any mcu reset occurs. 16.5.2 description of reset operation reset clears the tpmxsc register wh ich disables clocks to the tpm a nd disables timer overflow interrupts (toie=0). cpwms, msnb, msna, elsnb, and elsna are all cleared which configures all tpm channels for input-capture operation with the associated pins disconnect ed from i/o pin logic (so all mcu pins related to the tpm revert to general purpose i/o pins). 16.6 interrupts 16.6.1 general the tpm generates an optional interr upt for the main counter overflow a nd an interrupt for each channel. the meaning of channel interrupts depends on each channel?s mode of operation. if the channel is configured for input capture, the in terrupt flag is set ea ch time the selected input capture edge is recognized. if the channel is configur ed for output compare or pwm modes, the interrupt flag is set each time the main timer counter matches the va lue in the 16-bit channel value register.
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 289 all tpm interrupts are listed in table 16-8 which shows the interrupt name, the name of any local enable that can block the interrupt request from leaving the tpm and getting r ecognized by the separate interrupt processing logic. the tpm module will provide a high-tr ue interrupt signal. vectors and pr iorities are determined at chip integration time in the interrupt module so refer to the user?s guide for th e interrupt module or to the chip?s complete document ation for details. 16.6.2 description of interrupt operation for each interrupt source in the tpm, a flag bit is set upon recognition of the interrupt condition such as timer overflow, channel-input captur e, or output-compare events. this flag may be read (polled) by software to determine that the action has occurred, or an associated enab le bit (toie or chnie) can be set to enable hardware interrupt generation. while the interrupt enable bit is set, a static interr upt will generate whenever the associated interrupt flag equals one. the user?s software must perform a sequence of steps to clear the interrupt flag before retu rning from the interrupt-service routine. tpm interrupt flags are clear ed by a two-step process including a read of the flag bit while it is set (1) followed by a write of zero (0) to th e bit. if a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. 16.6.2.1 timer overflow in terrupt (tof) description the meaning and details of operation for tof interrupts varies slightly depending upon the mode of operation of the tpm system (gen eral purpose timing functions vers us center-aligned pwm operation). the flag is cleared by the two step sequence described above. 16.6.2.1.1 normal case normally tof is set when the timer counter ch anges from 0xffff to 0x0000. when the tpm is not configured for center-aligned pwm (cpwms=0), tof ge ts set when the timer c ounter changes from the terminal count (the value in th e modulo register) to 0x0000. this case corresponds to the normal meaning of counter overflow. table 16-8. interrupt summary interrupt local enable source description tof toie counter overflow set each time th e timer counter reaches its terminal count (at transition to next count value which is usually 0x0000) chnf chnie channel event an input capt ure or output compare event took place on channel n
MC9S08JM16 series data sheet, rev. 2 290 freescale semiconductor 16.6.2.1.2 center-aligned pwm case when cpwms=1, tof gets set when the timer c ounter changes directi on from up-counting to down-counting at the end of the terminal count (the value in the modul o register). in this case the tof corresponds to the end of a pwm period. 16.6.2.2 channel event interrupt description the meaning of channel interrupts depends on the channel?s current m ode (input-capture, output-compare, edge-aligned pwm, or center-aligned pwm). 16.6.2.2.1 input capture events when a channel is configured as an input capture channel, the elsnb:elsna control bits select no edge (off), rising edges, falling edges or any edge as the ed ge which triggers an input capture event. when the selected edge is detected, the interrupt flag is set. the flag is cleared by the two-step sequence described in section 16.6.2, ?description of interrupt operation .? 16.6.2.2.2 output compare events when a channel is configured as an output compare chan nel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. th e flag is cleared by the two-step sequence described section 16.6.2, ?description of interrupt operation .? 16.6.2.2.3 pwm end-of-duty-cycle events for channels configured for pwm operation there are two possibilities. when the channel is configured for edge-aligned pwm, the channel flag gets set when the timer counter matches the channel value register which marks the end of the active duty cycle period. wh en the channel is configured for center-aligned pwm, the timer count matches the channel value register twice during each pwm cycle. in this cpwm case, the channel flag is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value regi ster. the flag is cleared by the two-step sequence described section 16.6.2, ?description of interrupt operation .? 1. write to tpmxcnth:l registers ( section 16.3.2, ?tpm-counter registers (tpmxcnth:tpmxcntl) ) [se110-tpm case 7] any write to tpmxcnth or tpmxcntl registers in tpm v3 clears the tpm counter (tpmxcnth:l) and the prescaler co unter. instead, in the tpm v2 only the tpm counter is cleared in this case. 2. read of tpmxcnth:l registers ( section 16.3.2, ?tpm-counter registers (tpmxcnth:tpmxcntl) ) ? in tpm v3, any read of tpmxcnth:l register s during bdm mode returns the value of the tpm counter that is frozen. in tpm v2, if only one byte of the tpmxcnth:l registers was read before the bdm mode became active, th en any read of tpmxcnth:l registers during bdm mode returns the latched value of tpmxcn th:l from the read buffer instead of the frozen tpm counter value.
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 291 ? this read coherency mechanism is cleared in tpm v3 in bdm mode if there is a write to tpmxsc, tpmxcnth or tpmxcntl. instead, in these conditions the tpm v2 does not clear this read coherency mechanism. 3. read of tpmxcnvh:l registers ( section 16.3.5, ?tpm channel value registers (tpmxcnvh:tpmxcnvl) ) ? in tpm v3, any read of tpmxcnvh:l register s during bdm mode returns the value of the tpmxcnvh:l register. in tpm v2, if only one byte of the tpmxcnvh:l registers was read before the bdm mode became active, then a ny read of tpmxcnvh:l registers during bdm mode returns the latched value of tpmxcnth:l from the read buffer instead of the value in the tpmxcnvh:l registers. ? this read coherency mechanism is cleared in tpm v3 in bdm mode if there is a write to tpmxcnsc. instead, in this condition the tp m v2 does not clear this read coherency mechanism. 4. write to tpmxcnvh:l registers ? input capture mode ( section 16.4.2.1, ?input capture mode ) in this mode the tpm v3 does not allow the writes to tpmxcnvh:l registers. instead, the tpm v2 allows these writes. ? output compare mode ( section 16.4.2.2, ?output compare mode ) in this mode and if (clksb:clksa not = 0:0), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer at the next change of the tpm counter (end of the prescaler counting) after the se cond byte is written. instead, the tpm v2 always updates these registers when their second byte is written. ? edge-aligned pwm ( section 16.4.2.3, ?edge-aligned pwm mode ) in this mode and if (clksb:clksa not = 00), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer after that the both bytes we re written and when the tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. instead, the tpm v2 makes this update after that the both bytes were written and when the tpm counter changes from tpmxmodh:l to $0000. ? center-aligned pwm ( section 16.4.2.4, ?center-aligned pwm mode ) in this mode and if (clksb:clksa not = 00), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer after that the both bytes we re written and when the tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. instead, the tpm v2 makes this update after that the both bytes were written and when the tpm counter changes from tpmxmodh:l to (tpmxmodh:l - 1). 5. center-aligned pwm ( section 16.4.2.4, ?center-aligned pwm mode ) ? tpmxcnvh:l = tpmxmodh:l [se110-tpm case 1] in this case, the tpm v3 produces 100% duty cycle. instead, the tpm v2 produces 0% duty cycle. ? tpmxcnvh:l = (tpmxmodh:l - 1) [se110-tpm case 2]
MC9S08JM16 series data sheet, rev. 2 292 freescale semiconductor in this case, the tpm v3 produces almost 100% duty cycle. in stead, the tpm v2 produces 0% duty cycle. ? tpmxcnvh:l is changed from 0x0000 to a non-zero value [se110-tpm case 3 and 5] in this case, the tpm v3 waits for the start of a new pwm period to be gin using the new duty cycle setting. instead, the tpm v2 changes the channel output at the middle of the current pwm period (when the count reaches 0x0000). ? tpmxcnvh:l is changed from a non-zero value to 0x0000 [se110-tpm case 4] in this case, the tpm v3 finishes the curren t pwm period using the old duty cycle setting. instead, the tpm v2 finishes the current pw m period using the new duty cycle setting. 6. write to tpmxmodh:l re gisters in bdm mode ( section 16.3.3, ?tpm counter modulo registers (tpmxmodh:tpmxmodl) ) in the tpm v3 a write to tpmxsc register in bdm mode clears the write coherency mechanism of tpmxmodh:l registers. instead, in the tpm v2 this coherency mechanism is not cleared when there is a write to tpmxsc register.
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 293
MC9S08JM16 series data sheet, rev. 2 294 freescale semiconductor
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 295 chapter 17 universal serial bus device controller (s08usbv1) 17.1 introduction this chapter describes an universal serial bus device controller (s08usbv1) m odule that is based on the universal serial bus specification rev 2.0. the usb bu s is designed to replace existing bus interfaces such as rs-232, ps/2, and ieee 1284 for pc peripherals. the s08usbv1 module provides a single-chip soluti on for full-speed (12 mbps) usb device applica- tions, and integrates the required tran sceiver with serial interface engine (sie), 3.3 v regulator, endpoint ram and other control logics. 17.1.1 clocking requirements the s08usbv1 requires two clock sources, the 24 mhz bus clock and a 48 mhz reference clock. the 48 mhz clock is sourced directly from mcgout. to achieve the 48 mhz clock rate, the mcg must be configured properly for pll engaged external (pee) mode with an external crystal. for usb operation, examples of mcg c onfiguration using pee mode include: ? 2 mhz crystal ? rdiv = 000 and vdiv = 0110 ? 4 mhz crystal ? rdiv = 001 and vdiv = 0110 17.1.2 current consumpt ion in usb suspend in usb suspend mode, the s08usbv1 cu rrent consumption is limited to 500 a. when the usb device goes into suspend mode, the firmware typically en ters stop3 to meet the usb suspend requirements on current consumption. note enabling lvd increases current consum ption in stop3. consequently, when trying to satisfy usb suspend requireme nts, disabling lvd before entering stop3. 17.1.3 3.3 v regulator if using an external 3.3 v regulator as an input to v usb33 (only when usbvren = 0), the supply voltage, v dd , must not fall below th e input voltage at the v usb33 pin. if using the internal 3.3 v regulator (usbvren = 1), do not connect an external supply to the v usb33 pin. in this case, v dd must fall between 3.9 v and 5.5 v for the internal 3.3 v regulator to operate correctly.
chapter 17 universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 296 freescale semiconductor table 17-1. usbvren configuration usbvren 3.3 v regulator v dd supply voltage range 0 external 3.3 v regulator (as input to v usb33 pin) v usb33 v dd supply voltage 1 internal 3.3 v regulator (no external supply connected to v usb33 pin) 3.9 v v dd supply voltage 5.5 v
chapter 17 universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 297 figure 17-1. MC9S08JM16 series block di agram highlighting usb blocks and pins ptc1/sda ptc0/scl v ss v dd pte3/tpm1ch1 pte2/tpm1ch0 pta5,pta0 pte0/txd1 pte1/rxd1 ptd1/adp9/acmp? ptd0/adp8/acmp+ ptc5/rxd2 ptc4 ptc3/txd2 ptc2 port a port c port d port e 7-bit keyboard interrupt module (kbi) iic module (iic) 8-/16-bit serial peripheral interface module (spi16) user flash (in bytes) user ram (in bytes) on chip ice and debug module (dbg) MC9S08JM16 = 16,384 hcs08 core cpu bdc notes: 1. port pins are software configurable with pullup device if input port. 2. pin contains software configurable pullup/pulldown device if pullup irq is enabled (irqpe = 1). pulldown is enabled if risi ng edge detect is selected (irqedg = 1) 3. irq does not have a clamp diode to v dd . irq must not be driven above v dd . 4. pin contains integrated pullup device. 5. when pin functions as kbi (kbipen = 1) an d associated pin is configured to enable the pullup device, kbedgn can be used to rec onfigure the pullup as a pulldown device. 2-channel timer/pwm module (tpm2) ptb5/kbip5/adp5 port b pte5/mosi1 pte4/miso1 pte6/spsck1 pte7/ss1 hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd low-power oscillator multi-purpose clock generator (mcg) reset v ssad v ddad v refh analog-to-digital converter (adc) 4-channel timer/pwm module (tpm1) ptd7 2 ptb4/kbip4/adp4 ptg3/kbip7 ptg2/kbip6 port g 8-channel, 12-bit bkgd/ms ptf0/tpm1ch2 ptf1/tpm1ch3 port f ptf5/tpm2ch1 ptf4/tpm2ch0 ptf6 interface module (sci1) serial communications interface module (sci2) serial communications ptg0/kbip0 ptg1/kbip1 mc9s08jm8 = 8,192 v refl ptg4/xtal ptg5/extal irq/tpmclk rxd2 txd2 sda scl 6 kbipx kbipx tpmclk spsck1 ss1 miso1 mosi1 tpmclk tpm1ch1 tpm1ch0 rxd1 txd1 extal xtal 2 4 usb sie usb endpoint ram full speed usb transceiver usbdp usbdn miso2 ss2 spsck2 mosi2 ptb1/mosi2/adp1 ptb0/miso2/adp0 8-/16-bit serial peripheral interface module (spi2) real-time counter (rtc) ptb3/ss2 /adp3 ptb2/spsck2/adp2 tpm1chx 3 tpm2ch1 tpm2ch0 2 analog comparator (acmp) system usb 3.3 v voltage regulator v usb33 1024 acmpo acmp+ acmp? ptd2/kbip2/acmpo v ssosc
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 298 freescale semiconductor 17.1.4 features features of the usb module include: ? usb 2.0 compliant ? 12 mbps full-speed (fs) data rate ? usb data control logic: ? packet identification and decoding/generation ? crc generation and checking ? nrzi (non-return-to-zero i nverted) encoding/decoding ? bit-stuffing ? sync detection ? end-of-packet detection ? seven usb endpoints ? bidirectional endpoint 0 ? six unidirectional data endpoints conf igurable as interrupt, bulk, or isochronous ? endpoints 5 and 6 support double-buffering ?usb ram ? 256 bytes of buffer ram shared between system and usb module ? ram may be allocated as buffers for usb controller or extra system ram resource ? usb reset options ? usb module reset generated by mcu ? bus reset generated by the host, which triggers a cpu interrupt ? suspend and resume operations with remote wakeup support ? transceiver features ? converts usb differential voltages to digital logic signal levels ? on-chip usb pullup resistor ? on-chip 3.3 v regulator 17.1.5 modes of operation table 17-2. operating modes mode description stop1 usb module is not functional. before entering stop1, the internal usb voltage regulator and usb transceiver enter shutdown mode; therefore, the usb voltage regulator and usb transceiver must be disabled by firmware. stop2 usb module is not functional. before entering stop2, the internal usb voltage regulator and usb transceiver enter shutdown mode; therefore, the usb voltage regulator and usb transceiver must be disabled by firmware.
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 299 17.1.6 block diagram figure 17-2 is a block diagram of the usb module. figure 17-2. usb module block diagram stop3 the usb module is optionally available in stop3. a reduced current consumption mode may be required for usb suspend mode per usb specification rev. 2.0, and stop3 mode is useful for achieving lower current consumption for the mcu and hence the overall usb device. before entering stop3 via firmware, the user mu st ensure that the device settings are configured for stop3 to achieve usb suspend current consumption targets. the usb module is notified about entering suspend mode when the sleepf flag is set; this occurs after the usb bus is idle for 3 ms. the device usb suspend m ode current consumption leve l requirements are defined by the usb specification rev. 2.0 (500 a for low-power and 2.5 ma for high-power with remote-wakeup enabled). if usbresmen in usbctl0 is set, and a k-state (resume signaling) is detected on the usb bus, the lpresf bit in usbctl0 will be set. this triggers an asynchro nous interrupt that will wakeup the mcu from stop3 mode and enable clocks to the usb module. the usbresmen bit must then be cleared immediately after stop3 recovery to clear the lpresf flag bit. wait usb module is operational. table 17-2. operating modes (continued) mode description skyblue gasket ram arbitration usb ram 256 bytes irq local bus usbdp usbdn serial interface engine to interrupt controller peripheral bus usb controller xcvr vreg protocol and rate match v usb33 bvci target tx logic bvci initiator rx logic 48 mhz reference clock 24 mhz clock (bus clk) enable (sie) usbdp pullup buffer manager
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 300 freescale semiconductor 17.2 external signal description the usb module requires both data and power pins. table 17-3 describes each of the usb external pin 17.2.1 usbdp usbdp is the positive usb differ ential signal. in a usb peripheral applicati on, connect an external 33 1% resistor in series with this signal in orde r to meet the usb specif ication rev. 2.0 impedance requirement. 17.2.2 usbdn usbdn is the negative usb differential signal. in a usb peripheral application, connect an external 33 1% resistor in series with this signal in orde r to meet the usb specif ication, rev. 2.0 impedance requirement. 17.2.3 v usb33 v usb33 is connected to the on-chip 3.3 v voltage regul ator (vreg). v usb33 maintains an output voltage of 3.3 v and can only source enough current for usb internal transceiver (xcvr) and usb pullup resistor. if the vreg is disabled by software, the a pplication must input an external 3.3 v power supply to the usb module via v usb33 . 17.3 register definition this section describes the memory map and control/status registers for the usb module. table 17-3. usb external pins name port direction function reset state positive usb differential signal usbdp i/o differential usb signaling. high impedance negative usb differential signal usbdn i/o differential usb signaling. high impedance usb voltage regulator power pin v usb33 power 3.3 v usb voltage regulator output or 3.3 v usb transceiver/resistor supply input. ?
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 301 17.3.1 usb control re gister 0 (usbctl0) 17.3.2 peripheral id register (perid) the perid reads back the value of 0x04. this va lue is defined for the usb module peripheral. 76543210 r0 usbpu usbresmen lpresf 0 usbvren 0 usbphyen w usbreset r e s e t00000000 = unimplemented or reserved figure 17-3. usb transceiver and regul ator control register 0 (usbctl0) table 17-4. usbctl0 field descriptions field description 7 usbreset usb reset ? this bit generates a hard reset of the usb module, usbphyen and usbvregen bits will also be cleared. (need remember to restart usb transceiver and usb voltage regulator). when set to 1, this bit automatically clears when the reset occurs. 0 usb module normal operation 1 returns the usb module to its reset state 6 usbpu pull up source ? this bit determines the source of the pullup resistor on the usbdp line. 0 internal usbdp pullup resistor is disabled; the application can use an external pullup resistor 1 internal usbdp pullup resistor is enabled 5 usbresmen usb low-power resume event enable ? this bit, when set, enables the usb module to send an asynchronous wakeup interrupt to the mcu upon detecti on that the lpresf bit has been set, indicating a k-state on the usb bus. this bit must be set before entering low-power stop3 mode only after sleepf=1 (usb is entering suspend mode). it must be cleared immediately after stop3 recovery in order to clear the low-power resume flag. 0 usb asynchronous wakeup from suspend mode disabled 1 usb asynchronous wakeup from suspend mode enabled 4 lpresf low-power resume flag ? this bit becomes set in usb suspend mode if usbresmen=1 and a k-state is detected on the usb bus, indicating resume signaling while the device is in a low-power stop3 mode. this flag bit will trigger an asynchronous interrupt, which will wake the device from stop3. firmware must then clear the usbresmen bit in order to clear the lpresf bit. 0 no k-state detected on the usb bus while the device is in stop3 and the usb is suspended. 1 k-state detected on the usb bus when usbresmen=1, th e device is in stop3, and the usb is suspended. 2 usbvren usb voltage regulator enable ? this bit enables the on-chip 3.3 v usb voltage regulator. 0 on-chip usb voltage regulator is disabled (off mode) 1 on-chip usb voltage regulator is enabled for active or standby mode 0 usbphyen usb transceiver enable ? when the usb transceiver (xcvr) is disabled, usbdp and usbdn are hi-z. it is recommended that the xcvr be enabled before setting th e usben bit in the ctl regi ster. the firmware must ensure that the xcvr remains enabled when entering usb suspend mode. 0 on-chip xcvr is disabled 1 on-chip xcvr is enabled
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 302 freescale semiconductor 17.3.3 peripheral id comple ment register (idcomp) the idcomp reads back the complement of the peripheral id register. for the usb module peripheral this will be 0xfb. 17.3.4 peripheral revision register (rev) the rev reads back the value of the usb peripheral revision. 76543210 r 0 0 id5 id4 id3 id2 id1 id0 w r e s e t00000100 = unimplemented or reserved figure 17-4. peripheral id register (perid) table 17-5. perid field descriptions field description 5:0 id[5:0] peripheral configuration number ?this number is set to 0x04 and indicates that the peripheral is the full-speed usb module. 76543210 r 1 1 nid5 nid4 nid3 nid2 nid1 nid0 w r e s e t11111011 = unimplemented or reserved figure 17-5. peripheral id complement register (idcomp) table 17-6. idcomp field descriptions field description 5:0 nid[5:0] compliment id number ? one?s complement version of id[5:0]. 76543210 r rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 w r e s e t00000000 = unimplemented or reserved figure 17-6. peripheral revision register (rev)
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 303 17.3.5 interrupt status register (intstat) the intstat contains bits for each of the interrupt source within the usb module. each of these bits is qualified with its respective interrupt en able bits (see the interrupt enable re gister). all bits of the register are logically or'ed together to form a single interrupt source for the microcontroll er. once an interrupt bit has been set, it may only be cleared by writing a 1 to the respective interr upt bit. this regi ster will contain the value of 0x00 after a reset. table 17-7. rev field descriptions field description 8?0 rev[7:0] revision ? revision number of the usb module. 76543210 r stall f 0 resumef sleepf tokdnef softokf errorf usbrstf w r e s e t00000000 = unimplemented or reserved figure 17-8. interrupt status register (intstat) table 17-9. intstat field descriptions field description 7 stallf stall flag ? the stall interrupt is used in device mode. in device mode the stall flag is asserted when a stall handshake is sent by the serial interface engine (sie). 0 a stall handshake has not been sent 1 a stall handshake has been sent 5 resumef resume flag ? this bit is set 2.5 s after clocks to the usb module have restarted following resume signaling. it can be used to indicate remote wakeup signaling on the usb bus. this interrupt is enabled only when the usb module is about to enter suspend mode (usually when sleepf interrupt detected). 0 no resume observed 1 resume detected (k-state is observed on the usbdp/usbdn signals for 2.5 s) 4 sleepf sleep flag ? this bit is set if the usb module has detected a constant idle on the usb bus for 3 ms, indicating that the usb module will go into suspend mode. the sleep timer is reset by activity on the usb bus. 0 no constant idle state of 3 ms has been detected on the usb bus 1 a constant idle state of 3 ms has been detected on the usb bus 3 tokdnef token complete flag ? this bit is set when the current transaction is completed. the firmware must immediately read the stat register to determine the endpoint and bd informatio n. clearing this bit (by setting it to 1) causes the stat register to be cl eared or the stat fifo holding register to be loaded into the stat register. 0 no tokens being processed are complete 1 current token being processed is complete 2 softokf sof token flag ? this bit is set if the usb module has received a start of frame (sof) token. 0 the usb module has not received an sof token 1 the usb module has received an sof token
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 304 freescale semiconductor 17.3.6 interrupt enable register (intenb) the intenb contains enabling bits for each of the interrupt sour ces within the usb modu le. setting any of these bits will enable the respectiv e interrupt source in the intstat register. this register will contain the value of 0x00 after a reset, i.e. all interrupts disabled. 1 errorf error flag ? this bit is set when any of the error conditi ons within the errstat register has occurred. the firmware must then read the errstat regist er to determine the source of the error. 0 no error conditions within the errstat register have been detected 1 error conditions within the errstat register have been detected 0 usbrstf usb reset flag ?this bit is set when the usb module has decoded a valid usb reset. when asserted, this bit will inform the mcu to automatically write 0x00 to the address register and to enable endpoint 0. usbrstf is set once a usb reset has been detected for 2.5 s. it will not be asserted again until the usb reset condition has been removed, and then reasserted. 0 no usb reset observed 1 usb reset detected 76543210 r stall 0 resume sleep tokdne softok error usbrst w r e s e t00000000 figure 17-9. interrupt enable register (intenb) table 17-10. intenb field descriptions field description 7 stall stall interrupt enable ? setting this bit will enable stall interrupts. 0 interrupt disabled 1 interrupt enabled 5 resume resume interrupt enable ? setting this bit will enable resume interrupts. 0 interrupt disabled 1 interrupt enabled 4 sleep sleep interrupt enable ? setting this bit will enable sleep interrupts. 0 interrupt disabled 1 interrupt enabled 3 tokdne tokdne interrupt enable ? setting this bit will enable tokdne interrupts. 0 interrupt disabled 1 interrupt enabled 2 softok softok interrupt enable ? setting this bit will enable softok interrupts. 0 interrupt disabled 1 interrupt enabled table 17-9. intstat field descriptions (continued) field description
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 305 17.3.7 error interrupt status register (errstat) the errstat contains bits for each of the error s ources within the usb module. each of these bits corresponds to its respectiv e error enable bit (see section 17.3.8, ?error interr upt enable register (errenb) ?.) the result is or'ed together and sent to the error bit of the intstat register. once an interrupt bit has been set, it may only be cleared by writing a 1 to the corresponding flag bit. each bit is set as soon as the error condition is detected. thus, the interrupt will typically not correspond with the end of a token being processed. this register will contain the value of 0x00 after reset. 1 error error interrupt enable ? setting this bit will enable error interrupts. 0 interrupt disabled 1 interrupt enabled 0 usbrst usbrst interrupt enable ? setting this bit will enable usbrst interrupts. 0 interrupt disabled 1 interrupt enabled 76543210 r btserrf reserved buferrf btoerrf dfn8f crc16f crc5f piderrf w r e s e t00000000 figure 17-10. error interrupt status register (errstat) table 17-11. errstat field descriptions field description 7 btserrf bit stuff error flag ? a bit stuff error has been detected. if set, the corresponding packet will be rejected due to a bit stuff error. 0 no bit stuff error detected 1 bit stuff error flag set 5 buferrf buffer error flag ? this bit is set if the usb module has requested a memory access to read a new bd but has not been given the bus before the usb module needs to receive or transmit data. if processing a tx (in endpoint) transfer, this would cause a transmit data underfl ow condition. or if proce ssing an rx (out endpoint) transfer, this would cause a receive data overflow condition. th is bit is also set if a data packet to or from the host is larger than the buffer size that is allocated in the bd. in this case the data packet is truncated as it is put into buffer memory. 0 no buffer error detected 1 a buffer error has occurred 4 btoerrf bus turnaround error timeout flag ? this bit is set if a bus turnaround timeout error has occurred. the usb module uses a bus turnaround timer to keep track of th e amount of time elapsed between the token and data phases of a setup or out token or the data and hands hake phases of an in token. if more than 16-bit times are counted from the previous eop before a transi tion from idle, a bus turnaround timeout error will occur. 0 no bus turnaround timeout error has been detected 1 a bus turnaround timeout error has occurred table 17-10. intenb field descriptions (continued) field description
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 306 freescale semiconductor 17.3.8 error interrupt enab le register (errenb) 3 dfn8f data field error flag ? the data field received was not an interval of 8 bits. the usb specification specifies that the data field must be an integer number of bytes. if the data field was not an integer number of bytes, this bit will be set. 0 the data field was an integer number of bytes 1 the data field was not an integer number of bytes 2 crc16f crc16 error flag ? the crc16 failed. if set, the data packet was rejected due to a crc16 error. 0 no crc16 error detected 1 crc16 error detected 1 crc5f crc5 error flag ? this bit will detect a crc5 error in the token packets generated by the host. if set, the token packet was rejected due to a crc5 error. 0 no crc5 error detected 1 crc5 error detected, and the token packet was rejected. 0 piderrf pid error flag ? the pid check failed. 0 no pid check error detected 1 pid check error detected 76543210 r btserr 0 buferr btoerr dfn8 crc16 crc5 piderr w r e s e t00000000 figure 17-11. error interrupt enable register (errenb) table 17-12. errstat field descriptions field description 7 btserr btserr interrupt enable ? setting this bit will enable btserr interrupts. 0 interrupt disabled 1 interrupt enabled 5 buferr buferr interrupt enable ? setting this bit will enable buferr interrupts. 0 interrupt disabled 1 interrupt enabled 4 btoerr btoerr interrupt enable ? setting this bit will enable btoerr interrupts. 0 interrupt disabled 1 interrupt enabled 3 dfn8 dfn8 interrupt enable ? setting this bit will enable dfn8 interrupts. 0 interrupt disabled 1 interrupt enabled 2 crc16 crc16 interrupt enable ? setting this bit will enable crc16 interrupts. 0 interrupt disabled 1 interrupt enabled table 17-11. errstat field descriptions (continued) field description
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 307 17.3.9 status register (stat) the stat reports the transaction status within the usb module. when the mcu receives a tokdne interrupt, the stat is read to determine the status of the previous endpoint communication. the data in the status register is vali d only when the tokdnef interr upt flag is asserted. the st at register is actually a read window into a status fifo maintained by th e usb module. when the usb module uses a bd, it updates the status register . if another usb transacti on is performed before the tokdne interrupt is serviced, the usb module will store the status of the next transaction in the stat fifo. thus, the stat register is actually a four byte fifo which allows the microcontroll er to process one tr ansaction while the serial interface engine (sie) is processing the next . clearing the tokdnef bit in the intstat register causes the sie to update the stat regi ster with the contents of the next stat value. if the next data in the stat fifo holding register is valid, the sie will immediately reassert the tokdne interrupt. 1 crc5 crc5 interrupt enable ? setting this bit will enable crc5 interrupts. 0 interrupt disabled 1 interrupt enabled 0 piderr piderr interrupt enable ? setting this bit will enable piderr interrupts. 0 interrupt disabled 1 interrupt enabled 76543210 r endp[3:0] in odd 0 0 w r e s e t00000000 = unimplemented or reserved figure 17-12. status register (stat) table 17-13. stat field descriptions field description 7?4 endp[3:0] endpoint number ? these four bits encode the endpoint address that received or transmitted the previous token. this allows the microcontroller to determine wh ich bdt entry was updated by the last usb transaction. 0000 endpoint 0 0001 endpoint 1 0010 endpoint 2 0011 endpoint 3 0100 endpoint 4 0101 endpoint 5 0110 endpoint 6 table 17-12. errstat field descriptions (continued) field description
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 308 freescale semiconductor 17.3.10 control register (ctl) the ctl provides various control and conf iguration informati on for the usb module. 3 in in/out transaction ? this bit indicates whether the last bdt updated was for a transmit (in) transfer or a receive (out) data transfer. 0 last transaction was a receive (out) data transfer 1 last bdt updated was for transmit (in) transfer 2 odd odd/even transaction ?this bit indicates whether the last buffer descriptor updated was in the odd bank of the bdt or the even bank of the bdt, see earlier section for more information on bdt address generation. 0 last buffer descriptor updated was in the even bank 1 last buffer descriptor updated was in the odd bank 76543210 r tsuspend cresume oddrst usben w reset00000000 figure 17-13. control register (ctl) table 17-14. ctl field descriptions field description 5 tsuspend transaction suspend ? this bit is set by the serial interface engine (sie) when a setup token is received, allowing software to dequeue any pending packet transactions in the bdt before resuming token processing. the tsuspend bit informs the processor that the si e has disabled packet transmission and reception. clearing this bit allows the sie to continue token processing. 0 allows the sie to continue token processing 1 set by the sie when a setup token is received; sie has disabled packet transmission and reception. 2 cresume resume signaling ? setting this bit will allow the usb module to execute resume signaling. this will allow the usb module to perform remote wakeup. software must set cresume to 1 for the amount of time required by the usb specification rev. 2.0 and then clear it to 0. 0 do not execute remote wakeup 1 execute resume sig naling ? remote wakeup 1 oddrst odd reset ? setting this bit will reset all the buffer descriptor odd ping-pong bits to 0 which will then specify the even descriptor bank. this bit is used with double -buffered endpoints 5 and 6. this bit has no effect on endpoints 0 through 4. 0 do not reset 1 reset all the buffer descriptor o dd ping/pong bits to 0 wh ich will then specify the even descriptor bank 0 usben usb enable setting this bit will enable the usb module to operate. setting this bit causes the sie to reset all of its odd bits to the bdts. thus, setting th is bit will reset much of the logic in the sie. 0 disable the usb module 1 enable the usb module for operation, will not affect transceiver and vreg. table 17-13. stat field descriptions (continued) field description
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 309 17.3.11 address register (addr) the addr register contains the un ique 7-bit address the device will be recogni zed as through usb. the register is reset to 0x00 after the reset input has gone active or the usb modul e has decoded usb reset signaling. that will initialize the address regist er to decode address 0x00 as required by the usb specification. firmware will ch ange the value when it pro cesses a set_address request. 17.3.12 frame number regi ster (frmnuml, frmnumh) the frame number registers contains the 11-bit fr ame number. the frame number registers require two 8-bit registers to implement. the low order byte is contained in frmnuml, and the high order byte is contained in frmnumh. these registers are updated with the curr ent frame number whenever a sof token is received. 76543210 r0 addr6 addr5 addr4 addr3 addr2 addr1 addr0 w r e s e t00000000 figure 17-14. addres s register (addr) table 17-15. addr field descriptions field description 6?0 addr[6:0] usb address ? this 7-bit value defines the usb address that the usb module will decode 76543210 r frm7 frm6 frm5 frm4 frm3 frm2 frm1 frm0 w r e s e t00000000 = unimplemented or reserved figure 17-15. frame number register low (frmnuml) table 17-16. frmnuml field descriptions field description 7?0 frm[7:0] frame number ? these bits represent the low order bits of the 11 bit frame number.
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 310 freescale semiconductor 17.3.13 endpoint control register (epctln, n=0-6) the endpoint control registers c ontains the endpoint control bits (epctldis, eprxen, eptxen, and ephshk) for each endpoint available within the us b module for a decoded addr ess. these four bits define all of the control necessary for any one endpoint. the formats fo r these registers are shown in the tables below. endpoint 0 (endp0) is associated with control pipe 0 which is required by the usb for all functions. therefore, after a usbrst interrupt has be en received, the microcontroller must set epctl0 to contain 0x0d. 76543210 r00000f r m 1 0f r m 9f r m 8 w r e s e t00000000 = unimplemented or reserved figure 17-16. frame number register high (frmnumh) table 17-17. frmnumh field descriptions field description 2?0 frm[10:8] frame number ? these bits represent the high order bits of the 11-bit frame number. 76543210 r0 0 0 epctldis eprxen eptxen epstall ephshk w reset (ep0-6) 00000000 = unimplemented or reserved figure 17-17. endpoint control register (epctln) table 17-18. epctln field descriptions field description 4 epctldis endpoint control ? this bit defines if an endpoint is enabl ed and the direction of the endpoint. the endpoint enable/direction control is defined in table 17-19 . 3 eprxen endpoint rx enable ? this bit defines if an endpoint is enabled for out transfers. the endpoint enable/direction control is defined in ta b l e 1 7 - 1 9 . 2 eptxen endpoint tx enable ? this bit defines if an endpoint is enabled for in transfers. the endpoint enable/direction control is defined in ta b l e 1 7 - 1 9 .
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 311 17.4 functional description this section describes the functiona l behavior of the usb module. it documents data packet processing for endpoint 0 and data endpoints, usb suspend and re sume states, sof token pr ocessing, reset conditions and interrupts. 17.4.1 block descriptions figure 17-2 is the block diagram. the m odule?s sub-blocks and external signals are described in the following sections. the module invol ves several major blocks ? usb transceiver (xcvr), usb serial interface engine (sie), a 3.3 v re gulator (vreg), endpoint buffer mana ger, shared ram arbitration, usb ram and the skyblue gasket. 17.4.1.1 usb serial in terface engine (sie) the sie is composed of two major functions: tx logic and rx logic. these major functions are described below in more detail. the tx and rx logic are connected by a usb protocol engine which manages packet flow to and from the usb module. the sie is connected to the rest of the system via 1 epstall endpoint stall ? when set, this bit indicates that the endpoint is stalled. this bit has priority over all other control bits in the endpoint control register, but is only valid if eptxen=1 or eprxen=1. any access to this endpoint will cause the usb module to return a stall handshake. once an endpoint is stalled it requires intervention from the host controller. 0 endpoint n is not stalled 1 endpoint n is stalled 0 ephshk endpoint handshake ? this bit determines if the endpoint will perform handshaking during a transaction to the endpoint. this bit will generally be set unless the endpoint is isochronous. 0 no handshaking performed during a transaction to this endpoint (usually for isochronous endpoints) 1 handshaking performed during a transaction to this endpoint table 17-19. endpoint enable/direction control bit name endpoint enable/direction control 4 epctldis 3 eprxen 2 eptxen x00 disable endpoint x01 enable endpoint for in(tx) transfers only x10 enable endpoint for out(rx) transfers only 0 1 1 enable endpoint for in, out and setup transfers. 1 1 1 reserved table 17-18. epctln field descriptions (continued) field description
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 312 freescale semiconductor internal basic virtual component interface (bvci) compliant target and initiator buses. the bvci target interface is used to configure the usb sie and to provide st atus and interrupts to cp u. the bvci initiator interface provides the integrated dma controller access to the buffer descriptor tabl e (bdt), and transfers usb data to or from usb ram memory. 17.4.1.1.1 serial interface e ngine (sie) transmitter logic the sie transmitter logic has two prim ary functions. the first is to format the usb data packets that have been stored in the endpoint buffers. the second is to transmit data packets via the usb transceiver. all of the necessary usb data formatting is pe rformed by the sie transmitter logic, including: ? nrzi encoding ? bit-stuffing ? crc computation ? addition of the sync field ? addition of the end-of-packet (eop) the cpu typically places data in the endpoint buffers as part of the application. when the buffer is configured as an in buffer and the usb host requests a packet, the sie responds with a properly formatted data packet. the transmitter logic is also used to generate res ponses to packets received fr om the usb host. when a properly formatted packet is received from the usb host, the transmitter logic responds with the appropriate ack, nak or stall handshake. when the sie transmitter logic is transmitting data from the buffer space for a particular endpoint, cpu access to that endpoint buffe r space is not recommended. 17.4.1.1.2 serial interface engine (sie) receiver logic the sie receiver logic receives us b data and stores usb packets in usb ram for processing by the cpu and the application software. serial data from the tr ansceiver is converted to a byte-wide parallel data stream, checked for proper packet frami ng, and stored in the usb ram memory. received bitstream processing in cludes the following operations: ? decodes an nrzi usb serial data stream ? sync detection ? bit-stuff removal (and error detection) ? end-of-packet (eop) detection ? crc validation ?pid check ? other usb protocol layer checks. the sie receiver logic provi des error detection including: ? bad crc ? timeout detection for eop
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 313 ? bit stuffing violation if a properly formatted packet is re ceived, the receiver logi c initiates a handshake response to the host. if the packet is not decoded correctly due to bit stuff violation, crc error or othe r packet level problem, the receiver ignores it. the usb host will eventually ti me-out waiting for a response, and retransmit the packet. when the sie receiver logic is rece iving data in the buffer space for a particular endpoi nt, cpu access to that buffer space is not recommended. 17.4.1.2 mcu/memory interfaces 17.4.1.2.1 skyblue gasket the skyblue gasket connects the usb module to the soc internal peripheral bus. the gasket maps accesses to the endpoint buffer descript ors or the endpoint buffers into th e shared ram block, and it also maps accesses to the peripherals register set into th e serial interface engine (sie) register space. the skyblue gasket interface includes registers to c ontrol the usb transceiver and voltage regulator. 17.4.1.2.2 endpoint buffer manager each endpoint supported by the usb devi ce transmits data to and from buffers stored in the shared buffer memory. the serial interface engine (sie) uses a table of descriptors, the buffer descriptor table (bdt), which is also stored in the usb ra m to describe the characteristics of each endpoint. the endpoint buffer manager is responsible for mapping requests to access endpoint buffer de scriptors into physical addresses within the usb ram block. 17.4.1.2.3 ram arbitration the arbitration block allows access to the usb ram block from the s kyblue gasket block and from the sie. 17.4.1.3 usb ram the usb module includes 256 bytes of high speed ram, accessible by the usb serial interface engine (sie) and the cpu. the usb ram runs at twice th e speed of the bus clock to allow interleaved non-blocked access by the cpu and sie. the usb ram is used for storag e of the buffer descriptor table (bdt) and endpoint buffers. usb ram th at is not allocated for the bdt and endpoint buffers can be used as system memory. if the usb module is not enabled, then the entire usb ram may be used as unsecured system memory. 17.4.1.4 usb transceiver (xcvr) the usb transceiver is electrically compliant to the universal serial bus specification 2.0. this block provides the necessary 2-wire differential nrzi signaling for usb communicat ion. the transceiver is on-chip to provide a cost effectiv e single chip usb peripheral solution.
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 314 freescale semiconductor 17.4.1.5 usb on-chip voltage regulator (vreg) the on-chip 3.3 v regulator provides a stable power source to power the usb internal transceiver and provide for the termination of an internal or external pullup resistor. when the on- chip regulator is enabled, it requires a voltage supply input in the range from 3.9 v to 5.5 v, and th e voltage regulator output will be in the range of 3.0 v to 3.6 v. with a dedicated on-chip usb 3.3 v regulator and a separate power supply fo r the mcu, the mcu and usb can operate at different voltages (see the us b electricals regarding th e usb voltage regulator electrical characteristics). when the on-chip 3.3 v regulator is disa bled, a 3.3 v source must be provided through the v usb33 pin to power the usb transceiver. in this case, the power supply voltage to the mcu must not fall below the input voltage at the v usb33 pin. the 3.3 v regulator has 3 modes including: ? active mode ? this mode is entered when usb is active. current requirement is sufficient to power the transceiver and the usbdp pullup resistor. ? standby ? the voltage regulator standby mode is entered automati cally when the usb device is in suspend mode. when the usb device is forced into suspend mode by th e usb bus, the firmware must configure the mcu for stop3 mode. in sta ndby mode, the requirement is to maintain the usbdp pin voltage at 3.0 v to 3.6 v, with a 900 (worst-case) pullup. ? power off ? this mode is entered anytime when stop2 or stop1 is entered or when the voltage regulator is disabled. 17.4.1.6 usb on-chip usbdp pullup resistor the pullup resistor on the usbdp line required for fu ll-speed operation by the usb specification rev. 2.0 can be internal or external to the mcu, dependi ng on the application requirements. an on-chip pullup resistor, implemented as specified in the usb 2.0 re sistor ecn, is optionally available via firmware configuration. alternatively, this on-chip pullup re sistor can be disabled, and the usb module can be configured to use an external pullup resistor for the usbdp li ne instead. if using an external pullup resistor on the usbdp line, the resistor must comply with the requirements in the usb 2.0 resistor ecn found at http://www.usb.org. the usbpu bit in the usbctl0 register can be used to indicate if the pullup resistor is internal or external to the mcu. if usbpu is clear, the internal pullup resistor on usbdp is disabled, and an external usbdp pullup can be used. when using an external usbdp pullup, if the vol tage regulator is enabled, the v usb33 voltage output can be used with the usbdp pullup. while the use of the internal usbdp pullup resistor is generally recommended, the figure below shows th e usbdp pullup resistor configuration for a usb device using an external resistor tied to v usb33 .
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 315 figure 17-18. usbdp/usbdn pullup resi stor configuration for usb module 17.4.1.7 usb powering and us bdp pullup enable options the usb module provides a single-chip solution for us b device applications th at are self-powered or bus-powered. the usb device needs to know when it has a valid usb connection in order to enable or disable the pullup resistor on the usbdp line. for the usb module on this device, the pullup on usbdp is only applied when a valid vbus connection is sensed, as required by the usb specification. in bus-powered applications, system power must be derived from vbus . because vbus is only available when a valid usb connection from host to device is made, the vbus sensing is built-in, and the usbdp pullup can be enabled accordingly. with self-powered applicat ions, determining when a valid usb connect ion is made is different from that of bus-powered applications. in self-powered applications, vbus sensing must be built into the application. for inst ance, a kbi pin interrupt can be utilized (if available). when a valid vbus connection is made, the kbi interrupt can notif y the application that a valid usb connection is available, and the internal pullup resistor can be enabled using the usbpu bi t. if an external pullup resistor is used instead of the internal one, the vbus sensing mechanism must be included in the system design. table 17-20 summarizes the differences in enabling the usbdp pullup for different usb power modes. table 17-20. usbdp pullup enable for different usb power modes power usbdp pullup pullup enable bus power (built-in vbus sense) internal set usbpu bit external build into application self power (build vbus sense into application) internal set usbpu bit external build into application usbdp usbdn usb device v usb33 3.3 v r dppu
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 316 freescale semiconductor 17.4.2 buffer descriptor table (bdt) to efficiently manage usb endpoint communications, the usb module implements a buffer descriptor table (bdt) comprised of buffer desc riptors (bd) in the local usb ram. the bd entries provide status or control information for a corr esponding endpoint. the bd entries also provide an address to the endpoint?s buffer. a single bd for an endpoint direction requires 3-bytes. a detailed description of the bdt format is provided in the next sections. the software api intelligently ma nages buffers for the usb module by updating the bdt when needed. this allows the usb module to efficiently ha ndle data transmission an d reception, while the microcontroller performs communication overhead processing and other function dependent applications. because the buffers are shared between the microc ontroller and the usb module, a simple semaphore mechanism is used to distinguish who is allowed to update the bdt and buffers in buffer memory. a semaphore bit, the own bit, is cleared to 0 when the bd entry is owned by the microcontroller. the microcontroller is allowed read and write access to th e bd entry and the data buffer when the own bit is 0. when the own bit is set to 1, the bd entry and the data buffer are owned by the usb module. the usb module now has full read and writ e access and the microcontroller mu st not modify the bd or its corresponding data buffer. 17.4.2.1 multiple buffer descriptor table entries for a single endpoint every endpoint direction requires at least one three-byte buffer desc riptor entry. t hus, endpoint 0, a bidirectional control endpoint, require s one bdt entry for the in direct ion, and one for the out direction. using two bd entries also allows for double-bufferi ng. double-buffering bds allo ws the usb module to easily transfer data at the maximum throughput pr ovided by the usb module. double buffering allows the mcu to process one bd while the usb module is processing the other bd. to facilitate double-bufferi ng, two buffer descriptor (b d) entries are needed fo r each endpoint direction. one bd entry is the even bd and the other is the odd bd. 17.4.2.2 addressing buffer descriptor table entries the bdt addressing is hardwired into the module. the bdt occupies the first portion of the usb ram. to access endpoint data via the usb or mcu, the addressing mechanism of the buffer descriptor table must be understood. all enabled in and out e ndpoint bd entries are inde xed into the bdt to allow easy access via the usb module or the mcu. the figure belo w shows the usb ram organization. the figure shows that the first entries in the usb ram are dedicated to storage of the bdt entries - i.e. the first 30 bytes of the usb ram (0x00 to 0x1d) are used to implement the bdt.
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 317 when the usb module receives a usb token on an en abled endpoint, it interrogates the bdt. the usb module reads the corresponding endpoint bd entry and determines if it owns the bd and corresponding data buffer. 17.4.2.3 buffer descriptor formats the buffer descriptors (bds) are gro ups of registers that provide endpoi nt buffer control information for the usb module and the mcu. the bd s have different meanings base d on who is reading the bd in memory. the usb module uses the data st ored in the bds to determine: ? who owns the buffer in system memory ? data0 or data1 pid ? release own upon packet completion ? data toggle synchronization enable ? how much data to be transmitted or received ? where the buffer resides in the buffer ram. the microcontroller uses the data stored in the bds to determine: ? who owns the buffer in system memory ? data0 or data1 pid ? the received token pid table 17-21. usb ram organization usb ram offset usb ram description of contents 0x00 bdt endpoint 0 in endpoint 0, out endpoint 1 endpoint 2 endpoint 3 endpoint 4 endpoint 5, buffer even endpoint 5, buffer odd endpoint 6, buffer even 0x1d endpoint 6, buffer odd 0x1e reserved 0x1f reserved 0x20 0xff usb ram available for endpoint buffers
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 318 freescale semiconductor ? how much data was transmitted or received. ? where the buffer resides in buffer memory the bdt is composed of buffer descriptors (bd) whic h are used to define and control the actual buffers in the usb ram space. bds always occur as a 3-bytes block. see figure 17-19 for the bd example of endpoint 0 in start from usb ram offset 0x00. the format for the buffer descriptor is shown in table 17-22 . offset 7 6 5 4 3 2 1 0 0x00 r own data0/1 bdtkpid[3] bdtkpid[3] bd tkpid[1] bdtkpid[0] 0 0 w0 0 d t s b d t s t a l l 0x01 r bc[7:0] w 0x02 r epadr[9:4] w figure 17-19. buffer descriptor example table 17-22. buffer descriptor table fields field description own own ? this own bit determines who currently owns the buff er. the usb sie generally writes a 0 to this bit when it has completed a token. the usb module ignores all other fields in the bd when own=0. once the bd has been assigned to the usb module (own=1), the mcu must not change it in any way. this byte of the bd must always be the last byte the mcu (firmware) updates when it initializes a bd. although the hardware will not block the mcu from accessing the bd while owned by the usb sie, doing so may cause undefined behavior and is generally not recommended. 0 the mcu has exclusive access to the entire bd 1 the usb module has exclusive access to the bd data0/1 data toggle ? this bit defines if a data0 field (data0/1=0) or a data1 (data0/1=1) field was transmitted or received. it is unchanged by the usb module. 0 data 0 packe t 1 data 1 packet bdtkpid[3:0] the current token pid is written back to the bd by the usb module when a transfer completes. the values written back are the token pid values from the usb spec ification: 0x1 for an out token, 0x9 for and in token or 0xd for a setup token. dts data toggle synchronization ? this bit enables data toggle synchronization. 0 no data toggle synchronization is performed. 1 data toggle synchronization is performed. bdtstall bdt stall ? setting this bit will cause the usb module to issue a stall handshake if a token is received by the sie that would use the bdt in th is location. the bdt is not consumed by the sie (the own bit remains and the rest of the bd is unchanged) when the bdtstall bit is set. 0 bdt stall is disabled 1 usb will issue a stall handshake if a token is received by the sie that would use the bdt in this location
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 319 17.4.3 usb transactions when the usb module transmits or receives data, it will first compute the bdt address based on the endpoint number, data direction, and which buffer is being used (even or odd), then it will read the bd. once the bd has been read, and if the own bit equals 1, the se rial interface engine (s ie) will transfer the packet data to or receive the pack et data from the buffer pointed to by the epadr field of the bd. when the usb token is complete, the usb module will update the bdt and change the own bit to 0. the stat register is updated and the tokdne interrupt is set. when the micr ocontroller processes the tokdne interrupt, it reads the status register. this gives the microcontroller all the information it needs to process the endpoint. at this point the microcontro ller can allocate a new bd , so additional usb data can be transmitted or received for that e ndpoint, and it can process the previous bd. figure 17-20 shows a timeline for how a typical usb token would be processed. bc[7:0] byte count ? the byte count bits represent the 8-bit byte count. the usb module serial interface engine (sie) will change this field upon the completion of a rx tr ansfer with the byte count of the data received. note that while usb supports packets as large as 1023 byte s for isochronous endpoints, this module limits packet size to 64 bytes. epadr[9:4] endpoint address ? the endpoint address bits represent the upper 6 bits of the 10-bit buffer address within the module?s local usb ram. bits [3:0] of epadr are always zero, therefore the address of the buffer must always start on a 16-byte aligned address within the loca l ram. these bits are unchanged by the usb module. this is not the address of the memory on the system bus. epadr is relative to the start of the local usb ram. table 17-22. buffer descriptor table fields (continued) field description
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 320 freescale semiconductor figure 17-20. usb packet flow the usb has two sources of data overrun error: ? the memory latency to the local usb ram interf ace may be too high and cause the receive buffer to overflow. this is predominantly a hardware performance issue, us ually caused by transient memory access issues. ? the packet received may be larger than the negotiated maxpacket size. this is caused by a software bug. in the first case, the usb will respond with a nak or bus timeout (bto) as appropriate for the class of transaction. the btoerr bit will be set in the errstat register. depending on the values of the intenb and errenb register, usb mo dule may assert an interrupt to notify the cpu of the error. in device mode the bdt is not written back nor is the tokdne interrupt triggered because it is assumed that a second attempt will be queue d at future time and will succeed. in the second case of oversized data packets, the usb specification assumes correct software drivers on both sides. the overrun is not due to memory latency but to a lack of space to put the excess data. nak'ing the packet will likely cause anothe r retransmission of the already oversized packet data. in response to oversized packets, the usb module will still ack the packet for non-isochronous transfers. the data written to memory is clipped to the maxpacket si ze so as not to corrupt the buffer space. the usb module will assert the buferrf bit of the errstat re gister (which could trigger an interrupt, as above) and a tokdne interrupt fails. the bdtkpid field of the bdt will not be ?1111? because the buferrf is not due to latency. the packet leng th field written back to the bdt will be the maxpacket value to represent the length of the clipped da ta actually written to memory. from here the software can decide an = usb host = function usb rst sof usbrst interrupt generated sof interrupt generated setup token data ack tokdne interrupt generated in token data ack out token data ack tokdne interrupt generated tokdne interrupt generated
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 321 appropriate course of action for future transacti ons ? stalling the endpoint , canceling the transfer, disabling the endpoint, etc. 17.4.4 usb packet processing packet processing for a usb device consists of mana ging buffers for in (to the usb host) and out (to the usb device) transactions. packet processing is further divided into request processing on endpoint 0, and data packet proce ssing on the data endpoints. 17.4.4.1 usb data pipe processing data pipe processing is essentially a buffer management task. the firmware is responsible for managing the shared buffer ram to ensure that a bd is always ready for the hardware to process (own bit = 1). the device allocates buffers within the shared ram, sets up the buffer de scriptors, and wait s for interrupts. on receipt of a tokdne interrupt, the firmware reads the stat register to dete rmine which endpoint is affected, then reads the corresponding bdt entry to determine what to do next. when processing data packets, firmware is responsible for managing the size of the packet buffers to be in compliance with the usb specifi cation, and the physical limitations of this module. pa cket sizes up to 64 bytes are supported on all endpoints. isochronous endpoints also can onl y specify packet sizes up to 64 bytes. firmware is also responsible for setting the appropriat e bits in the bdt. for mo st applications using bulk packets (control, bulk, and interrupt-type transfers), th e firmware will set the dt s, bc and ep adr fields for each bd. for isochronous packets, firmware will set bc a nd epadr fields. in all cases, firmware will set the own bit to enable th e endpoint for data transfers. 17.4.4.2 request proc essing on endpoint 0 in most cases, commands to the usb device are dir ected to endpoint 0. the host uses the ?standard requests? described in chapter 9 of the usb specifi cation to enumerate and c onfigure the device. class drivers or product specific drivers running on the host send class (hid, ma ss storage, imaging) and vendor specific commands to the device on endpoint 0. usb requests always follow a specific format: ? host sends a setup token, follow ed by an 8-byte setup packet, a nd the device hardware can send a handshake packet. ? if the setup packet specifies a da ta phase, the host and device may tr ansfer up to 64 kbytes of data (either in or out, not both). ? the request is terminated by a status phase. device firmware monitors the intstat and stat registers, the e ndpoint 0 buffer descriptors (bd?s), and the contents of the setup packet to correctly execute the host?s request. the flow for processing endpoint 0 requests is as follows: 1. allocate 8-byte buffers for endpoint 0 out.
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 322 freescale semiconductor 2. create bdt entries for endpoint 0 out, and set the dts and own bits to 1. 3. wait for interrupt tokdne. 4. read stat register. ? the status register must show endpoint 0, rx. if it does not, then assert the epstall bit in the endpoint control register. 5. read endpoint 0 out bd. ? verify that the token type is a setup token. if it is not, then assert the epstall bit in the endpoint control register. 6. decode and process the setup packet. ? if the direction field in the setup packet indicates an out transfer, then process the out data phase to receive exactly the number of bytes speci fied in the wlength field of the setup packet. ? if the direction field in the setup packet indicate s an in transfer, then process the in data phase to deliver no more than the number of bytes speci fied in the wlength field. note that it is common for the host to request more bytes than it needs, expecting th e device to only send as much as it needs to. 7. after processing the data phase (if there was one), create a zero-byte st atus phase transaction. ? this is accomplished for an out data phase (in status phase) by setting the bc to 0 in the next bd, while also setting own=1. for an in data phase (out status phase), the host will send a zero-byte packet to the device. ? firmware can verify completion of the data phase by verifying the receiv ed token in the bd on receipt of the tokdne interrupt. if the data phase was of type in, then the status phase token will be out. if the data phase was of type out, then the st atus phase token will be in. 17.4.4.3 endpoint 0 exception conditions the usb includes a number of error ch ecking and recovery mechanisms to ensure reliable data transfer. one such exception occurs when the host sends a setu p packet to a device, a nd the host never receives the acknowledge handshake from the device. in this case, the host will retry the setup packet. endpoint 0 request handlers on the device must be aware of the possibil ity that after receiving a correct setup packet, they could receive another setup p acket before the data phase actually begins. 17.4.5 start of frame processing the usb host allocates time in 1.0 ms chunks called ?frames? for the purposes of packet scheduling. the usb host starts each frame with a broadcast token called sof (start of frame) that includes an 11-bit sequence number. the toksof interrupt is used to notify firmware when an sof token was received. firmware can read the current frame num ber from the frmnuml/frmnumh registers. in general, the sof interrupt is only monitored by devices using isochronous endpoints to help ensure that the device and host remain synchronized.
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 323 17.4.6 suspend/resume the usb supports a single low-power mode called suspe nd. getting into and out of the suspend state is described in the following sections. 17.4.6.1 suspend the usb host can put a single device or the entire bus into the suspend state at any time. the mcu supports suspend mode for lo w power. suspend mode will be entered when the usb data lines are in the idle state for more than 3 ms. en try into suspend mode is announced by the sleepf bit in the intstat register. per the usb specification, a low-power bus-powered usb device is requi red to draw less than 500 a in suspend state. a high-power device that supports remote wakeup and has its remote wake-up feature enabled by the host can draw up to 2.5 ma of current. after the initial 3 ms idle, the usb device will reach this state within 7 ms. this low-cu rrent requirement means that firmware is responsible for entering stop3 mode once the sleepf flag has been set and before the usb module has been placed in the suspend state. on receipt of resume signaling from the usb, the module can generate an as ynchronous interrupt to the mcu which brings the device out of stop mode and wakes up the clocks. setting the usbresmen bit in the usbctl0 register immediately after the sleepf bit is set enab les this asynchronous notification feature. the usb resume signaling will then cause the lpresf bit to be set, indicating a low-power suspend resume, which will wa ke the cpu from stop3 mode. during normal operation, while the host is sending sof packets, the usb module will not enter suspend mode. 17.4.6.2 resume there are three ways to get out of the suspend stat e. when the usb module is in suspend state, the resume detection is active even if all th e clocks are disabled and the mcu is in stop3 mode. the mcu can be activated from the suspend state by normal bus activity, a usb rese t signal, or upstream resume (remote wakeup). 17.4.6.2.1 host initiated resume the host signals a resume from suspe nd by initiating resume signaling (k st ate) for at least 20 ms followed by a standard low-speed eop signal. this 20 ms ensure s that all devices in the usb network are awakened. after resuming the bus, the host must begin sending bus traffic within 3 ms to prevent the device from re-entering suspend mode. depending on the power mode the device is in while suspended, the notification for a host initiated resume will be different: ? run mode ? resume must be se t after sleepf becomes set to enable the resumef interrupt. then, upon resume signaling, the resumef interrupt will trigger after a k-state has been observed on the usbdp/usbdn lines for 2.5 s. ? stop3 mode ? usbresmen must be set after sleepf becomes set to arm the lpresf bit. then, upon a k-state on the bus while the device is in stop3 mode, the lpresf bit will be set,
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 324 freescale semiconductor indicating a resume from low-power suspend. this will trigger an asynchronous interrupt to wake the cpu from stop3 mode and resu me clocks to the usb module. note as a precaution, after lpresf is set, firmware must check the state of the usb bus to see if the k-st ate was a result of a tran sient event and not a true host-initiated resume. if this is the ca se, then the device can drop back into stop3 if necessary. to do this, the resume interrupt can be enabled in conjunction with the usbresmen featur e. then, after lpresf is set, and a k-state is still detected approximate ly 2.5 s after clocks have restarted, firmware can check that the resumef interrupt has triggered, indicating resume signaling from the host. 17.4.6.2.2 usb reset signaling reset can wake a device from the suspend state. 17.4.6.2.3 remote wakeup the usb device can send a resume ev ent to the host by writing to the cre sume bit. firmware must first set the bit for the time period required by the usb specification rev. 2.0 (section 7.1.7.7) and then clear it to 0. 17.4.7 resets the module supports multiple types of resets. the first is a bus reset generated by the usb host, the second is a module reset generated by the mcu. 17.4.7.1 usb bus reset at any time, the usb host may issue a reset to one or all of the devices attached to the bus. a usb reset is defined as a period of single ended ze ro (se0) on the cable for greater than 2.5 s. when the device detects reset signaling, it resets itself to the unconfigured state, and sets its usb address zero. the usb host uses reset signaling to force one or all connected devices into a known st ate prior to commencing enumeration. the usb module responds to reset signaling by asserting the usbrst in terrupt in the intstat register. software is required to service this interr upt to ensure correct operation of the usb. 17.4.7.2 usb module reset usb module resets are initiated on-chip. during a m odule reset, the usb module is configured in the default mode. the usb module can also be forced into its reset state by setting the usbreset bit in the usbctl0 register. the default mode includes the following settings: ? interrupts masked. ? usb clock enabled ? usb voltage re gulator disabled
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 325 ? usb transceiver disabled ? usbdp pullup disabled ? endpoints disabled ? usb address register set to zero 17.4.8 interrupts interrupts from the intstat register signif y events which occur during normal operation ? usb start of frame tokens (toksof), packet completion (tok dne), usb bus reset (usb rst), endpoint errors (error), suspend and resume (sleep and resume), and endpoint stalled (stall). the errstat interrupts carry information about sp ecific types of errors, which is needed on an application specific basis. using errstat, an application can de termine exactly why a packet transfer failed ? due to crc error, pid check error and so on. both registers are maskable via the intenb and errenb registers. the intstat and errstat are used to signal interrupts in a two- level structure. unmasked interrupt s from the errstat register are reported in the intstat register. note that the interrupt registers work in concert with the stat register. on receipt of an intstat interrupt, software can check the stat register and determine which bdt entry was affected by the transaction.
universal serial bus device controller (s08usbv1) MC9S08JM16 series data sheet, rev. 2 326 freescale semiconductor
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 327 chapter 18 development support 18.1 introduction this chapter describes the si ngle-wire background debug mode (bdm), which uses the on-chip background debug controller (bdc) modul e, and the independent on-chip real-time in-circuit emulation (ice) system, which uses th e on-chip debug (dbg) module. 18.1.1 forcing active background the method for forcing active background mode depe nds on the specific hcs08 derivative. for the MC9S08JM16 series, you can force active background mode by holding the bkgd pin low as the mcu exits the reset condition independent of what caused the reset. if no debug pod is connected to the bkgd pin, the mcu will always reset into normal operating mode.
development support MC9S08JM16 series data sheet, rev. 2 328 freescale semiconductor 18.1.2 features features of the bdc module include: ? single pin for mode selection and background communications ? bdc registers are not located in the memory map ? sync command to determine target communications rate ? non-intrusive commands for memory access ? active background mode comma nds for cpu register access ? go and trace1 commands ? background command can wake cpu from stop or wait modes ? one hardware address breakpoint built into bdc ? oscillator runs in stop mode, if bdc enabled ? cop watchdog disabled while in active background mode features of the ice system include: ? two trigger comparators: two address + read/write (r/w) or one full address + data + r/w ? flexible 8-word by 16-bit fifo (first-in, first-out) buffe r for capture information: ? change-of-flow addresses or ? event-only data ? two types of breakpoints: ? tag breakpoints for instruction opcodes ? force breakpoints for any address access ? nine trigger modes: ? basic: a-only, a or b ? sequence: a then b ? full: a and b data, a and not b data ? event (store data): event- only b, a then event-only b ? range: inside range (a address b), outside range (address < a or address > b) 18.2 background debug controller (bdc) all mcus in the hcs08 family contain a single-wire background debug interface that supports in-circuit programming of on-chip nonvolatile me mory and sophisticated non-intrus ive debug capabilities. unlike debug interfaces on earlier 8-bit mcus, this system does not interfere with normal application resources. it does not use any user memory or locations in the memory map and does not share any on-chip peripherals. bdc commands are divided into two groups: ? active background mode commands require that the target mcu is in active background mode (the user program is not running). active background mode commands al low the cpu registers to be read or written, and allow the user to trace one user instruction at a time, or go to the user program from active background mode.
development support MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 329 ? non-intrusive commands can be executed at any time even while the user?s program is running. non-intrusive commands allow a user to read or wr ite mcu memory locations or access status and control registers within the background debug controller. typically, a relatively s imple interface pod is used to translat e commands from a host computer into commands for the custom serial interface to the single-wire bac kground debug system. depending on the development tool vendor, this interface pod may use a sta ndard rs-232 serial port, a parallel printer port, or some other type of communicati ons such as a universal serial bu s (usb) to communicate between the host pc and the pod. the pod typically connects to th e target system with ground, the bkgd pin, reset , and sometimes v dd . an open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target syst em or to control startup of a target system before the on-chip nonvolatile memory has be en programmed. sometimes v dd can be used to allow the pod to use power from the target system to a void the need for a separa te power supply. however, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. figure 18-1. bdm tool connector 18.2.1 bkgd pin description bkgd is the single-wire background debug interface pin. the primary function of this pin is for bidirectional serial communi cation of active background mode commands and data. during reset, this pin is used to select between starting in active background mode or starting the us er?s application program. this pin is also used to request a timed sync respons e pulse to allow a host deve lopment tool to determine the correct clock frequency for b ackground debug serial communications. bdc serial communications use a cu stom serial protocol first introduced on the m68hc12 family of microcontrollers. this protocol a ssumes the host knows the communication clock rate that is determined by the target bdc clock rate. all communication is in itiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. commands and data are sent most significant bit first (msb first). for a detailed descript ion of the communications protocol, refer to section 18.2.2, ?communication details .? if a host is attempting to communi cate with a target mcu that ha s an unknown bdc clock rate, a sync command may be sent to the target mcu to request a timed sync res ponse signal from wh ich the host can determine the correct communication speed. bkgd is a pseudo-open-drain pin and there is an on-chip pullup so no ex ternal pullup resistor is required. unlike typical open-drain pins, the ex ternal rc time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. the custom prot ocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmfu l drive level conflicts. refer to section 18.2.2, ?communication details ,? for more detail. 2 4 6 no connect 5 no connect 3 1 reset bkgd gnd v dd
development support MC9S08JM16 series data sheet, rev. 2 330 freescale semiconductor when no debugger pod is connected to the 6-pin bdm interface connector, the internal pullup on bkgd chooses normal operating mode . when a debug pod is connected to bkgd it is possible to force the mcu into active background mode after reset. the speci fic conditions for forci ng active background depend upon the hcs08 derivative (refer to the introduction to this developm ent support section). it is not necessary to reset the target mcu to communi cate with it through the background debug interface. 18.2.2 communication details the bdc serial interface requires the external contro ller to generate a falling edge on the bkgd pin to indicate the start of each bit time. the external cont roller provides this falling edge whether data is transmitted or received. bkgd is a pseudo-open-drain pin that can be driven either by an extern al controller or by the mcu. data is transferred msb first at 16 bdc clock cycles pe r bit (nominal speed). th e interface times out if 512 bdc clock cycles occur between falling edges from the host. any bdc command that was in progress when this timeout occurs is aborted without affecti ng the memory or operating mode of the target mcu system. the custom serial protocol requires the debug pod to know the target bdc communication clock speed. the clock switch (clksw) control bit in the bdc status and c ontrol register allows th e user to select the bdc clock source. the bdc clock source can either be the bus or the alternate bdc clock source. the bkgd pin can receive a high or low level or transmit a high or lo w level. the following diagrams show timing for each of these cases. interface timing is synchronous to clocks in the target bdc, but asynchronous to the external host. the internal bdc clock signal is shown for reference in counting cycles.
development support MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 331 figure 18-2 shows an external host trans mitting a logic 1 or 0 to the bkgd pin of a target hcs08 mcu. the host is asynchronous to the target so there is a 0- to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. ten target bdc clock cycles later, the target senses the bit level on the bkgd pin. typically, the host actively driv es the pseudo-open-drain bkgd pin during host-to-target transmissions to speed up rising edges. because the target does not drive the bkgd pin during the host-to-target transmission period, there is no need to tr eat the line as an open-drain signal during this period. figure 18-2. bdc ho st-to-target serial bit timing earliest start target senses bit level 10 cycles synchronization uncertainty bdc clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time of next bit
development support MC9S08JM16 series data sheet, rev. 2 332 freescale semiconductor figure 18-3 shows the host receiving a logic 1 from th e target hcs08 mcu. because the host is asynchronous to the target mcu, th ere is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the perceived star t of the bit time in the target mcu. the host holds the bkgd pin low long enough for the target to recognize it (at least two target bdc cycles). the host must release the low drive before the target mcu drives a brie f active-high speedup pulse seven cycles after the perceived start of the bit time. the host must sample the bit level about 10 cycles after it started the bit time. figure 18-3. bdc target-to-host serial bit timing (logic 1) host samples bkgd pin 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu speedup pulse perceived start of bit time high-impedance high-impedance high-impedance bkgd pin r-c rise 10 cycles earliest start of next bit
development support MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 333 figure 18-4 shows the host receiving a logic 0 from th e target hcs08 mcu. because the host is asynchronous to the target mcu, th ere is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by th e target mcu. the host initiates the bit time but the target hcs08 finishes it. because the target wants the host to receive a l ogic 0, it drives the bkgd pin low for 13 bdc clock cycles, then briefly drives it high to speed up the rising edge. the host samples the bit level about 10 cycles after starting the bit time. figure 18-4. bdm target-to-host serial bit timing (logic 0) 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu drive and perceived start of bit time high-impedance bkgd pin 10 cycles speed-up pulse speedup pulse earliest start of next bit host samples bkgd pin
development support MC9S08JM16 series data sheet, rev. 2 334 freescale semiconductor 18.2.3 bdc commands bdc commands are sent se rially from a host computer to the bkgd pin of the target hcs08 mcu. all commands and data are sent msb-first using a cust om bdc communicat ions protocol. active background mode commands require that the target mcu is currently in the active background mode while non-intrusive commands may be issued at any time whether the target mcu is in active background mode or running a user application program. table 18-1 shows all hcs08 bdc commands, a shorthand de scription of their codi ng structure, and the meaning of each command. coding structure nomenclature this nomenclature is used in table 18-1 to describe the coding stru cture of the bdc commands. commands begin with an 8-bit hexadeci mal command code in the host-to-target direction (most signi ficant bit first) / = separates parts of the command d = delay 16 target bdc clock cycles aaaa = a 16-bit address in the host-to-target direction rd = 8 bits of read data in the target-to-host direction wd = 8 bits of write data in the host-to-target direction rd16 = 16 bits of read data in the target-to-host direction wd16 = 16 bits of write data in the host-to-target direction ss = the contents of bdcscr in th e target-to-host direction (status) cc = 8 bits of write data for bdcscr in the host-to-target direction (control) rbkp = 16 bits of read data in the target -to-host direction (fro m bdcbkpt breakpoint register) wbkp = 16 bits of write data in the host-to-tar get direction (for bdcb kpt breakpoint register)
development support MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 335 table 18-1. bdc command summary command mnemonic active bdm/ non-intrusive coding structure description sync non-intrusive n/a 1 1 the sync command is a special operation that does not have a command code. request a timed reference pulse to determine target bdc communication speed ack_enable non-intrusive d5/d enable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. ack_disable non-intrusive d6/d disable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. background non-intrusive 90/d enter active background mode if enabled (ignore if enbdm bit equals 0) read_status non-intrusive e4/ss r ead bdc status from bdcscr write_control non-intrusive c4/cc write bdc controls in bdcscr read_byte non-intrusive e0/aaaa/d/rd r ead a byte from target memory read_byte_ws non-intrusive e1/aaaa/d/ss/ rd read a byte and report status read_last non-intrusive e8/ss/rd re-read byte from address just read and report status write_byte non-intrusive c0/aaaa/wd/d write a byte to target memory write_byte_ws non-intrusiv e c1/aaaa/wd/d/ss write a byte and report status read_bkpt non-intrusive e2/rbkp read bdcbkpt breakpoint register write_bkpt non-intrusive c2/wbkp write bdcbkpt breakpoint register go active bdm 08/d go to execute the user application program starting at the address currently in the pc trace1 active bdm 10/d trace 1 user instruction at the address in the pc, then return to active background mode taggo active bdm 18/d same as go but enable external tagging (hcs08 devices have no external tagging pin) read_a active bdm 68/d/rd read accumulator (a) read_ccr active bdm 69/d/rd read condition code register (ccr) read_pc active bdm 6b/d/rd16 read program counter (pc) read_hx active bdm 6c/d/rd16 read h and x register pair (h:x) read_sp active bdm 6f/d/rd16 read stack pointer (sp) read_next active bdm 70/d/rd increment h:x by one then read memory byte located at h:x read_next_ws active bdm 71/d/ss/rd increment h:x by one then read memory byte located at h:x. re port status and data. write_a active bdm 48/wd/d write accumulator (a) write_ccr active bdm 49/wd/d write condition code register (ccr) write_pc active bdm 4b/wd16/d write program counter (pc) write_hx active bdm 4c/wd16/d write h and x register pair (h:x) write_sp active bdm 4f/wd16/d write stack pointer (sp) write_next active bdm 50/wd/d increment h:x by one, then write memory byte located at h:x write_next_ws active bdm 51/wd/d/ss increment h:x by one, then write memory byte located at h:x. also report status.
development support MC9S08JM16 series data sheet, rev. 2 336 freescale semiconductor the sync command is unlike other bdc commands because the host does not necessarily know the correct communications speed to us e for bdc communications until afte r it has analyzed the response to the sync command. to issue a sync command, the host: ? drives the bkgd pin low for at least 128 cycles of the slowest possible bdc clock (the slowest clock is normally the reference oscill ator/64 or the self-clocked rate/64.) ? drives bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the fastest clock in the system.) ? removes all drive to the bkgd pin so it reverts to high impedance ? monitors the bkgd pin for the sync response pulse the target, upon detectin g the sync request fr om the host (which is a much longer low time than would ever occur during norma l bdc communications): ? waits for bkgd to re turn to a logic high ? delays 16 cycles to allow the host to stop driving the high speedup pulse ? drives bkgd low for 128 bdc clock cycles ? drives a 1-cycle high speedup pulse to force a fast rise time on bkgd ? removes all drive to the bkgd pin so it reverts to high impedance the host measures the low time of this 128-cycle sync res ponse pulse and determines the correct speed for subsequent bdc communications. typically, the hos t can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 18.2.4 bdc hardware breakpoint the bdc includes one relatively simple hardware br eakpoint that compares the cpu address bus to a 16-bit match value in the bdcbkpt register. this brea kpoint can generate a forced breakpoint or a tagged breakpoint. a forced breakpoint causes the cpu to enter active background mode at the first instruction boundary following any access to the breakpoint address. the tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the cpu will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. this implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. the breakpoint enable (bkpten ) control bit in the bdc status and control re gister (bdcscr) is used to enable the breakpoint logic (bkpten = 1). when bkpten = 0, its default value after reset, the breakpoint logic is di sabled and no bdc breakpoints are requested regardless of the values in other bdc breakpoint registers and control bits. the force/tag select (fts) control bit in bdcscr is used to select forced (fts = 1) or tagged (fts = 0) type breakpoints. the on-chip debug module (dbg ) includes circuitry for two additional hardware breakpoints that are more flexible than the simple breakpoint in the bdc module.
development support MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 337 18.3 on-chip debug system (dbg) because hcs08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have be en built onto the chip with the mcu. the debug system consists of an 8-stage fifo that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture. the system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage fifo. the debug module includes control and status regist ers that are accessible in the user?s memory map. these registers are located in the high register space to avoid using valuable direct page memory space. most of the debug module?s functions are used during development, a nd user programs rarely access any of the control and status registers for the debug modul e. the one exception is that the debug system can provide the means to implement a fo rm of rom patching. this topic is discussed in greater detail in section 18.3.6, ?hardware breakpoints .? 18.3.1 comparators a and b two 16-bit comparators (a and b) ca n optionally be qualified with the r/w signal and an opcode tracking circuit. separate control bits a llow you to ignore r/w for each compar ator. the opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opc ode at the specified address is actually executed as opposed to onl y being read from memory into th e instruction queue. the comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. comparators are disabled temp orarily during all bdc accesses. the a comparator is always associated with the 16- bit cpu address. the b comparator compares to the cpu address or the 8-bit cpu data bus, depending on the trigger mode selected. because the cpu data bus is separated into a read data bus and a write data bus, the rwaen and rwa control bits have an additional purpose, in full address pl us data comparisons they are used to decide which of these buses to use in the comparator b data bus comparisons. if rwaen = 1 (enabled) and rwa = 0 (write), the cpu?s write data bus is used. otherwise, the cpu?s read data bus is used. the currently selected trigger mode determines what the debugger logi c does when a comparator detects a qualified match condition. a match can cause: ? generation of a breakpoint to the cpu ? storage of data bus values into the fifo ? starting to store change-of-flow addre sses into the fifo (begin type trace) ? stopping the storage of change-of-flow a ddresses into the fifo (end type trace) 18.3.2 bus capture informat ion and fifo operation the usual way to use the fifo is to setup the trigger mode and other cont rol options, then arm the debugger. when the fifo has filled or the debugger has stopped storing data into the fifo, you would read the information out of it in the order it was stored into the fifo . status bits indicate the number of words of valid information that are in the fifo as data is stored into it. if a trace run is manually halted by writing 0 to arm before the fifo is full (cnt = 1:0:0:0), the inform ation is shifted by one position and
development support MC9S08JM16 series data sheet, rev. 2 338 freescale semiconductor the host must perform ((8 ? cnt) ? 1) dummy reads of the fifo to advance it to the first significant entry in the fifo. in most trigger modes, the information stored in the fifo consists of 16-bit change-of-flow addresses. in these cases, read dbgfh then dbgfl to get one coherent word of info rmation out of th e fifo. reading dbgfl (the low-order byte of the fifo data port) causes the fifo to shift so the next word of information is available at the fifo data port. in the event-only trigger modes (see section 18.3.5, ?trigger modes ? ), 8-bit data information is stored in to the fifo. in these cases, the high- order half of the fifo (dbgfh) is not used and data is read out of the fifo by simply reading dbgfl. ea ch time dbgfl is read, the fifo is shifted so the next data value is av ailable through the fifo data port at dbgfl. in trigger modes where the fifo is storing change -of-flow addresses, there is a delay between cpu addresses and the input side of th e fifo. because of this delay, if the trigger event itself is a change-of-flow address or a change-o f-flow address appears during the ne xt two bus cycles after a trigger event starts the fifo, it will not be saved into the fifo. in the case of an end-trace, if the trigger event is a change-of-flow, it will be saved as the last change-of-flow entry for that debug run. the fifo can also be used to generate a profile of executed instruction addresses when the debugger is not armed. when arm = 0, reading dbgfl causes the addr ess of the most-recently fetched opcode to be saved in the fifo. to use the prof iling feature, a host debugger would re ad addresses out of the fifo by reading dbgfh then dbgfl at regul ar periodic intervals. the first eight values would be discarded because they correspond to the eight dbgfl reads needed to initially fill the fifo. additional periodic reads of dbgfh and dbgfl return delayed information about executed instructions so the host debugger can develop a profile of executed instruction addresses. 18.3.3 change-of-flow information to minimize the amount of informati on stored in the fifo, only informat ion related to in structions that cause a change to the normal sequential execution of in structions is stored. w ith knowledge of the source and object code program stor ed in the target system, an external debugger system can reconstruct the path of execution through many instruct ions from the change -of-flow information stored in the fifo. for conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the a ddress of the conditional br anch opcode). because bra and brn instructions are not conditional, these events do not cause change-o f-flow information to be stored in the fifo. indirect jmp and jsr instruct ions use the current contents of the h: x index register pair to determine the destination address, so the debug system stores the r un-time destination address for any indirect jmp or jsr. for interrupts, rti, or rts, the destination address is stored in the fifo as change-of-flow information. 18.3.4 tag vs. force breakpoints and triggers tagging is a term that refers to identifying an instruc tion opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the cpu. this distinction is important because any change-of-flow from a jump, bran ch, subroutine call, or interrupt causes some instructions that have been fetched into the in struction queue to be thrown away without being executed.
development support MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 339 a force-type breakpoint wa its for the current instruction to fi nish and then acts upon the breakpoint request. the usual action in respons e to a breakpoint is to go to ac tive background mode rather than continuing to the next instruction in the user application program. the tag vs. force terminolo gy is used in two contexts within the debug module. the first context refers to breakpoint requests from the debug module to the cp u. the second refers to match signals from the comparators to the debugger control logi c. when a tag-type break request is sent to the cpu, a signal is entered into the instruction queue along with the opc ode so that if/when this opcode ever executes, the cpu will effectively replace the tagged opcode with a bgnd opcode so the cpu goes to active background mode rather than executi ng the tagged instruction. when the trgsel control bit in the dbgt register is set to select tag-type operation, the output from comparator a or b is qualified by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. there is se parate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. 18.3.5 trigger modes the trigger mode controls the overa ll behavior of a debug run. the 4-bi t trg field in th e dbgt register selects one of nine trigger modes. when trgsel = 1 in the dbgt regi ster, the output of the comparator must propagate through an opcode tracking circuit before triggering fifo actions. the begin bit in dbgt chooses whether the fi fo begins storing data wh en the qualified trigger is detected (begin trace), or the fifo stores data in a circular fashion from the time it is armed unt il the qualified trigger is detected (end trigger). a debug run is started by wr iting a 1 to the arm bit in the dbgc register, which sets the armf flag and clears the af and bf flags and the cnt bits in dbgs. a be gin-trace debug run ends when the fifo gets full. an end-trace run ends when the selected trigger event occurs. any debug run can be stopped manually by writing a 0 to arm or dbgen in dbgc. in all trigger modes except event- only modes, the fifo stores change-of-flow addresses. in event-only trigger modes, the fifo stores data in the low-order eight bits of the fifo. the begin control bit is ignored in event-only tri gger modes and all such debug runs are begin type traces. when trgsel = 1 to select opcode fetch triggers, it is not n ecessary to use r/w in comparisons because opcode tags would only apply to opcode fetches that are always read cycles. it would also be unusual to specify trgsel = 1 while using a full m ode trigger because the opcode value is normally known at a particular address. the following trigger mode descripti ons only state the primary comparator conditions that lead to a trigger. either comparator can usually be further quali fied with r/w by setting rwaen (rwben) and the corresponding rwa (rwb) value to be matched against r/w. the si gnal from the comparator with optional r/w qualification is used to request a cpu breakpoint if brken = 1 and tag determines whether the cpu request will be a tag request or a force request.
development support MC9S08JM16 series data sheet, rev. 2 340 freescale semiconductor a-only ? trigger when the address matc hes the value in comparator a a or b ? trigger when the address matches either the value in comparator a or the value in comparator b a then b ? trigger when the address matches the value in comparator b but only after the address for another cycle matched the value in comparator a. there can be any num ber of cycles after the a match and before the b match. a and b data (full mode) ? this is called a full mode because address, data, a nd r/w (optionally) must match within the same bus cycle to cause a tri gger event. comparator a ch ecks address, the low byte of comparator b checks data, and r/w is checked against rwa if rwaen = 1. the high-order half of comparator b is not used. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the pur pose of issuing the tag request to the cpu and the cpu breakpoint is issued when th e comparator a address matches. a and not b data (full mode) ? address must match comparator a, data must not match the low half of comparator b, and r/w mu st match rwa if rwaen = 1. all three conditions must be met within the same bus cycle to cause a trigger. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the pur pose of issuing the tag request to the cpu and the cpu breakpoint is issued when th e comparator a address matches. event-only b (store data) ? trigger events occur each time the address matches the value in comparator b. trigger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. a then event-only b (store data) ? after the address has matched the value in comparator a, a trigger event occurs each time the address ma tches the value in comparator b. tr igger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. inside range (a address b) ? a trigger occurs when the address is greater than or equal to the value in comparator a and less than or equal to the value in comparator b at the same time. outside range (address < a or address > b) ? a trigger occurs when the a ddress is either less than the value in comparator a or greater than the value in comparator b.
development support MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 341 18.3.6 hardware breakpoints the brken control bit in the dbgc register may be set to 1 to allow any of the trigger conditions described in section 18.3.5, ?trigger modes ,? to be used to gene rate a hardware breakpoint request to the cpu. tag in dbgc controls whether the breakpoint reque st will be treated as a tag-type breakpoint or a force-type breakpoint. a tag breakpoint causes the current opcode to be marked as it ente rs the instruction queue. if a tagged opcode reaches the end of the pipe, th e cpu executes a bgnd in struction to go to active background mode rather than execut ing the tagged opcode. a force-type breakpoint causes the cpu to finish the current instruction and then go to active background mode. if the background mode has not been enabled (enbdm = 1) by a serial write_control command through the bkgd pin, the cpu will execute an swi instruction instead of going to active background mode. 18.4 register definition this section contains the descriptions of the bdc and dbg registers and control bits. refer to the high-page register summary in the device overview chapter of this data sheet for the absolute address assignments for all dbg regist ers. this section refers to registers and control bits only by their names. a freescale-provided equate or header file is used to tr anslate these names into the appropriate absolute addresses. 18.4.1 bdc registers and control bits the bdc has two registers: ? the bdc status and control regist er (bdcscr) is an 8-bit regist er containing cont rol and status bits for the background debug controller. ? the bdc breakpoint match register (bdcbkpt ) holds a 16-bit breakpoint match address. these registers are accessed with dedicated serial bdc commands and are not located in the memory space of the target mcu (so they do not have a ddresses and cannot be a ccessed by user programs). some of the bits in the bdcscr ha ve write limitations; otherwise, thes e registers may be read or written at any time. for example, the enbdm control bit may not be written while the mcu is in active background mode. (this prevents th e ambiguous condition of the contro l bit forbidding active background mode while the mcu is already in active background mode.) also, the four status bits (bdmact, ws, wsf, and dvf) are read-only status indicators and can never be wr itten by the write_control serial bdc command. the clock switch (clksw) control bit may be r ead or written at any time.
development support MC9S08JM16 series data sheet, rev. 2 342 freescale semiconductor 18.4.1.1 bdc status and c ontrol register (bdcscr) this register can be read or written by serial bdc commands (read_status and write_control) but is not accessible to user programs because it is not located in the normal memory map of the mcu. 76543210 r enbdm bdmact bkpten fts clksw ws wsf dvf w normal reset 00000000 reset in active bdm: 11001000 = unimplemented or reserved figure 18-5. bdc status and control register (bdcscr) table 18-2. bdcscr register field descriptions field description 7 enbdm enable bdm (permit active background mode) ? typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the deb ug host resets the target and remains 1 until a normal reset clears it. 0 bdm cannot be made active (non-intrusive commands still allowed) 1 bdm can be made active to allow active background mode commands 6 bdmact background mode active status ? this is a read-only status bit. 0 bdm not active (user application program running) 1 bdm active and waiting for serial commands 5 bkpten bdc breakpoint enable ? if this bit is clear, the bdc breakpoint is disabled and the fts (force tag select) control bit and bdcbkpt match register are ignored. 0 bdc breakpoint disabled 1 bdc breakpoint enabled 4 fts force/tag select ? when fts = 1, a breakpoint is request ed whenever the cpu address bus matches the bdcbkpt match register. when fts = 0, a match between the cpu address bus and the bdcbkpt register causes the fetched opcode to be tagg ed. if this tagged opcode ever reache s the end of the instruction queue, the cpu enters active background mode rather than executing the tagged opcode. 0 tag opcode at breakpoint address and enter active background mode if cpu attempts to execute that instruction 1 breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 clksw select source for bdc communications clock ? clksw defaults to 0, which selects the alternate bdc clock source. 0 alternate bdc clock source 1 mcu bus clock
development support MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 343 18.4.1.2 bdc breakpoint match register (bdcbkpt) this 16-bit register holds the address for the hard ware breakpoint in the bdc. the bkpten and fts control bits in bdcscr are used to enable and configure the breakpoint logi c. dedicated serial bdc commands (read_bkpt and write_bk pt) are used to read and writ e the bdcbkpt register but is not accessible to user programs because it is not located in the normal memory map of the mcu. breakpoints are normally set while the target mcu is in active background mode before running the user application program. for additional information about setup and use of the hardware breakpoint logic in the bdc, refer to section 18.2.4, ?bdc hardware breakpoint .? 18.4.2 system background debug force reset register (sbdfr) this register contains a single write-only contro l bit. a serial background mode command such as write_byte must be used to write to sbdfr. attemp ts to write this register from a user program are ignored. reads always return 0x00. figure 18-6. system background debug force reset register (sbdfr) 2 ws wait or stop status ? when the target cpu is in wait or stop mode, most bdc commands cannot function. however, the background command can be used to force t he target cpu out of wait or stop and into active background mode where all bdc commands work. whenever the host forces the target mcu into active background mode, the host must issue a read_status command to check that bdmact = 1 before attempting other bdc commands. 0 target cpu is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 target cpu is in wait or stop mode, or a backgro und command was used to change from wait or stop to active background mode 1 wsf wait or stop failure status ? this status bit is set if a memory a ccess command failed due to the target cpu executing a wait or stop instruction at or about the same time. the usual recovery strategy is to issue a background command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (typically , the host would restore cpu registers and stack values and re-execute the wait or stop instruction.) 0 memory access did not conflict with a wait or stop instruction 1 memory access command failed because the cpu entered wait or stop mode 0 dvf data valid failure status ? this status bit is not used in the MC9S08JM16 series because it does not have any slow access memory. 0 memory access did not conflict with a slow memory access 1 memory access command failed because cpu was not finished with a slow memory access 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background mode debug commands, not from user programs. r e s e t00000000 = unimplemented or reserved table 18-2. bdcscr register field descriptions (continued) field description
development support MC9S08JM16 series data sheet, rev. 2 344 freescale semiconductor 18.4.3 dbg registers and control bits the debug module includes nine bytes of register spac e for three 16-bit register s and three 8-bit control and status registers. these registers are located in the high register space of the normal memory map so they are accessible to normal applic ation programs. these re gisters are rarely if ever accessed by normal user application programs with the possible ex ception of a rom patching mechanism that uses the breakpoint logic. 18.4.3.1 debug comparator a high register (dbgcah) this register contains compare value bits for the high- order eight bits of comparat or a. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 18.4.3.2 debug comparator a low register (dbgcal) this register contains compare value bits for the low- order eight bits of comparator a. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 18.4.3.3 debug comparator b high register (dbgcbh) this register contains compare value bits for the high- order eight bits of comparat or b. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 18.4.3.4 debug comparator b low register (dbgcbl) this register contains compare value bits for the low- order eight bits of comparator b. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 18.4.3.5 debug fifo high register (dbgfh) this register provides read- only access to the high-order ei ght bits of the fifo. writes to this register have no meaning or effect. in the event- only trigger modes, the fifo only st ores data into the low-order byte of each fifo word, so this regist er is not used and will read 0x00. reading dbgfh does not cause the fifo to shift to the next word. when reading 16-bit words out of the fifo, read dbgfh before reading dbgfl because reading dbgfl causes the fifo to advance to the next word of information. table 18-3. sbdfr register field description field description 0 bdfr background debug force reset ? a serial active background mode command such as write_byte allows an external debug host to force a target system reset. writing 1 to this bit forc es an mcu reset. this bit cannot be written from a user program.
development support MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 345 18.4.3.6 debug fifo low register (dbgfl) this register provides read- only access to the low-order ei ght bits of the fifo. writes to this register have no meaning or effect. reading dbgfl causes the fifo to shift to the ne xt available word of information. when the debug module is operating in event-only modes, only 8-bit data is stored into th e fifo (high-order half of each fifo word is unused). when readi ng 8-bit words out of the fifo, simp ly read dbgfl repeatedly to get successive bytes of data from the fifo. it is n?t necessary to read dbgfh in this case. do not attempt to read data from th e fifo while it is still armed (after arming but before th e fifo is filled or armf is cleared) because the fifo is prevented from advancing during reads of dbgfl. this can interfere with normal sequenci ng of reads from the fifo. reading dbgfl while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the fifo. by reading dbgfh then dbgfl periodical ly, external host software can develop a prof ile of program execution. after eight reads from the fifo, the ninth read will return the information that was stored as a result of the first read. to use the profiling feature, read the fifo eight times without using the data to prime the sequence and then begi n using the data to get a delayed picture of what addresses were be ing executed. the information stored into the fifo on reads of dbgfl (while the fifo is not armed) is the address of the most-recently fetched opcode.
development support MC9S08JM16 series data sheet, rev. 2 346 freescale semiconductor 18.4.3.7 debug control register (dbgc) this register can be read or written at any time. 76543210 r dbgen arm tag brken rwa rwaen rwb rwben w reset00000000 figure 18-7. debug control register (dbgc) table 18-4. dbgc register field descriptions field description 7 dbgen debug module enable ? used to enable the debug module. dbgen cannot be set to 1 if the mcu is secure. 0dbg disabled 1 dbg enabled 6 arm arm control ? controls whether the debugger is comparing and storing information in the fifo. a write is used to set this bit (and armf) and completion of a debug run automatically clears it. any debug run can be manually stopped by writing 0 to arm or to dbgen. 0 debugger not armed 1 debugger armed 5 tag tag/force select ? controls whether break requests to the cpu will be tag or force type requests. if brken = 0, this bit has no meaning or effect. 0 cpu breaks requested as force type requests 1 cpu breaks requested as tag type requests 4 brken break enable ? controls whether a trigger event will generate a break request to the cpu. trigger events can cause information to be stored in the fifo without generating a break request to the cpu. for an end trace, cpu break requests are issued to the cpu when the comparat or(s) and r/w meet the trigger requirements. for a begin trace, cpu break requests are issued when the fi fo becomes full. trgsel does not affect the timing of cpu break requests. 0 cpu break requests not enabled 1 triggers cause a break request to the cpu 3 rwa r/w comparison value for comparator a ? when rwaen = 1, this bit determines whether a read or a write access qualifies comparator a. when rwaen = 0, rw a and the r/w signal do not affect comparator a. 0 comparator a can only match on a write cycle 1 comparator a can only match on a read cycle 2 rwaen enable r/w for comparator a ? controls whether the level of r/w is considered for a comparator a match. 0 r/w is not used in comparison a 1 r/w is used in comparison a 1 rwb r/w comparison value for comparator b ? when rwben = 1, this bit determines whether a read or a write access qualifies comparator b. when rwben = 0, rw b and the r/w signal do not affect comparator b. 0 comparator b can match only on a write cycle 1 comparator b can match only on a read cycle 0 rwben enable r/w for comparator b ? controls whether the level of r/w is considered for a comparator b match. 0 r/w is not used in comparison b 1 r/w is used in comparison b
development support MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 347 18.4.3.8 debug trigger register (dbgt) this register can be read any time , but may be written only if arm = 0, except bits 4 and 5 are hard-wired to 0s. 76543210 r trgsel begin 00 trg3 trg2 trg1 trg0 w r e s e t00000000 = unimplemented or reserved figure 18-8. debug trigger register (dbgt) table 18-5. dbgt regist er field descriptions field description 7 trgsel trigger type ? controls whether the match outputs from com parators a and b are qualified with the opcode tracking logic in the debug module. if trgsel is set, a match signal from comparat or a or b must propagate through the opcode tracking logic and a trigger event is on ly signalled to the fifo logi c if the opcode at the match address is actually executed. 0 trigger on access to compare address (force) 1 trigger if opcode at compare address is executed (tag) 6 begin begin/end trigger select ? controls whether the fifo starts filling at a trigger or fills in a circular manner until a trigger ends the capture of informati on. in event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 data stored in fifo until trigger (end trace) 1 trigger initiates data storage (begin trace) 3:0 trg[3:0] select trigger mode ? selects one of nine triggering modes, as described below. 0000 a-only 0001 a or b 0010 a then b 0011 event-only b (store data) 0100 a then event-only b (store data) 0101 a and b data (full mode) 0110 a and not b data (full mode) 0111 inside range: a address b 1000 outside range: address < a or address > b 1001 ? 1111 (no trigger)
development support MC9S08JM16 series data sheet, rev. 2 348 freescale semiconductor 18.4.3.9 debug status register (dbgs) this is a read-onl y status register. 76543210 r af bf armf 0 cnt3 cnt2 cnt1 cnt0 w r e s e t00000000 = unimplemented or reserved figure 18-9. debug status register (dbgs) table 18-6. dbgs register field descriptions field description 7 af trigger match a flag ? af is cleared at the start of a debug run and indicates whether a trigger match a condition was met since arming. 0 comparator a has not matched 1 comparator a match 6 bf trigger match b flag ? bf is cleared at the start of a debug run and indicates whether a trigger match b condition was met since arming. 0 comparator b has not matched 1 comparator b match 5 armf arm flag ? while dbgen = 1, this status bit is a read-only im age of arm in dbgc. this bit is set by writing 1 to the arm control bit in dbgc (while dbgen = 1) and is automatically cleared at the end of a debug run. a debug run is completed when the fifo is full (begin trac e) or when a trigger event is detected (end trace). a debug run can also be ended manually by writing 0 to arm or dbgen in dbgc. 0 debugger not armed 1 debugger armed 3:0 cnt[3:0] fifo valid count ? these bits are cleared at the start of a debu g run and indicate the number of words of valid data in the fifo at the end of a debug run. the value in cnt does not decrement as data is read out of the fifo. the external debug host is responsible for keeping trac k of the count as information is read out of the fifo. 0000 number of valid words in fifo = no valid data 0001 number of valid words in fifo = 1 0010 number of valid words in fifo = 2 0011 number of valid words in fifo = 3 0100 number of valid words in fifo = 4 0101 number of valid words in fifo = 5 0110 number of valid words in fifo = 6 0111 number of valid words in fifo = 7 1000 number of valid words in fifo = 8
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 349 appendix a electrical characteristics a.1 introduction this appendix contains electrical and timi ng specifications for the MC9S08JM16 series of microcontrollers available at the time of publication. a.2 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a better understanding, the following classi fication is used and the parameters are tagged accordingly in the tabl es where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. a.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond th e limits specified in table a-2 may affect device reliability or cause permanent damage to the de vice. for functional operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ). table a-1. paramete r classifications p those parameters are guaranteed during produ ction testing on each individual device. c those parameters are achieved by the design charac terization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations.
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 350 freescale semiconductor a.4 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and it is user-deter mined rather than being controlled by the mcu design. in order to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. ex cept in cases of unusuall y high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. table a-2. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to 5.8 v input voltage v in ?0.3 to v dd + 0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1 , 2 , 3 1 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the m cu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. i d 25 ma maximum current into v dd i dd 120 ma storage temperature t stg ?55 to 150 c table a-3. thermal characteristics num c rating symbol value unit temp. code 1 t operating temperature range (packaged) t a ?40 to 85 cc 2 d maximum junction temperature t j 135 c 3t thermal resistance single layer board ? 32-pin lqfp 48-pin qfn 44-pin lqfp four layer board (2s2p) ? 32-pin lqfp 48-pin qfn 44-pin lqfp ja 81 83 70 53 29 48 c/w ?
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 351 the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. a-1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglecte d. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. a-2 solving equation a-1 and equation a-2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. a-3 where k is a constant pertaining to the particular part. k can be determined from equation a-3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of t j and p d can be obtained by solving equation a-1 and equation a-2 iteratively for any value of t a . a.5 esd protection and latch-up immunity although damage from electrostatic di scharge (esd) is much less comm on on these devices than on early cmos circuits, normal handling preca utions must be used to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can with stand exposure to reasonable levels of static without suffer ing any permanent damage. all esd testing is in conformity with aec-q100 stress test qualification for automotive grade integrated circuits . during the device qualification, esd stre sses were performed for the human body model (hbm) and the char ge device model (cdm). a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is perf ormed per the applicable device specification at room temperature followed by hot te mperature, unless specified otherwise in the device specification. table a-4. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulse per pin ? 3 latch-up minimum input voltage limit ? ?2.5 v maximum input voltage limit ? 7.5 v
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 352 freescale semiconductor a.6 dc characteristics this section includes information about power supply requirements, i/o pin characteristics, and power supply current in various operating modes. table a-5. esd and latch-up protection characteristics num rating symbol min max unit 1 human body model (hbm) v hbm 2000 ? v 2 charge device model (cdm) v cdm 500 ? v 3 latch-up current at t a = 85 ci lat 100 ? ma table 7. dc characteristics num c parameter symbol min typical 1 max. unit 1 operating voltage 2 2.7 ? 5.5 v 2p output high voltage ? low drive (ptxdsn = 0) 5 v, i load = ?4 ma 3 v, i load = ?2 ma 5 v, i load = ?2 ma 3 v, i load = ?1 ma v oh v dd ? 1.5 v dd ? 1.5 v dd ? 0.8 v dd ? 0.8 ? ? ? ? ? ? ? ? v output high voltage ? high drive (ptxdsn = 1) 5 v, i load = ?15 ma 3 v, i load = ?8 ma 5 v, i load = ?8 ma 3 v, i load = ?4 ma v dd ? 1.5 v dd ? 1.5 v dd ? 0.8 v dd ? 0.8 ? ? ? ? ? ? ? ? 3p output low voltage ? low drive (ptxdsn = 0) 5 v, i load = 4 ma 3 v, i load = 2 ma 5 v, i load = 2 ma 3 v, i load = 1 ma v ol ? ? ? ? ? ? ? ? 1.5 1.5 0.8 0.8 v output low voltage ? high drive (ptxdsn = 1) 5 v, i load = 15 ma 3 v, i load = 8 ma 5 v, i load = 8 ma 3 v, i load = 4 ma ? ? ? ? ? ? ? ? 1.5 1.5 0.8 0.8 4 p output high current ? max. total i oh for all ports 5 v 3 v i oht ? ? ? ? 100 60 ma 5 p output low current ? max. total i ol for all ports 5 v 3 v i olt ? ? ? ? 100 60 ma 6 c input high voltage; all digital inputs 5 v 3 v v ih 0.65 v dd 0.70 v dd ??v c input low voltage; all digital inputs v il ? ? 0.35 v dd 7 c input hysteresis; all digital inputs v hys 0.06 v dd mv 8 9 c input leakage current (per pin); input only pins |i in |? 0.1 1 a 10 p hi-z (off-state) leakage current (per pin) |i oz |? 0.1 1 a
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 353 11 p internal pullup resistors 3 r pu 20 45 65 k 12 p internal pulldown resistors 4 r pd 20 45 65 k 13 t internal pullup resistor to usbdp (to v usb33 ) idle transmit r pupd 900 1425 1300 2400 1575 3090 k 14 d dc injection current 5 6 7 8 single pin limit v in > v dd v in < v ss total mcu limit, includes sum of all stressed pins v in > v dd v in < v ss i ic 0 0 ? ? 2 ?0.2 ma 0 0 ? ? 25 ?5 ma 15 d input capacitance; all non-supply pins c in ?? 8pf 16 d ram retention voltage v ram ?0.61.0v 17 d por re-arm voltage v por 0.9 1.4 2.0 v 18 d por re-arm time t por 10 ? ? s 19 p low-voltage detection threshold ? high range v dd falling v dd rising v lvd 1 3.9 4.0 4.0 4.1 4.1 4.2 v p low-voltage detection threshold ? low range v dd falling v dd rising v lvd 0 2.48 2.54 2.56 2.62 2.64 2.70 v 20 p low-voltage warning threshold ? high range 1 v dd falling v dd rising v lv w 3 4.5 4.6 4.6 4.7 4.7 4.8 v 21 c low-voltage warning threshold ? high range 0 v dd falling v dd rising v lv w 2 4.2 4.3 4.3 4.4 4.4 4.5 v 22 p low-voltage warning threshold low range 1 v dd falling v dd rising v lv w 1 2.84 2.90 2.92 2.98 3.00 3.06 v 23 c low-voltage warning threshold ? low range 0 v dd falling v dd rising v lv w 0 2.66 2.72 2.74 2.80 2.82 2.88 v 24 25 t low-voltage inhibit reset/recover hysteresis +5 v +3 v v hys ? ? 100 60 ? ? mv mv 26 c bandgap voltage reference factory trimmed at v dd = 5.0 v, temp = 25 c v bg 1.19 1.20 1.21 v 1 typical values are based on characterization data at 25 c unless otherwise stated. 2 maximum is highest voltage that por is guaranteed. table 7. dc characteristics (continued) num c parameter symbol min typical 1 max. unit
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 354 freescale semiconductor figure a-1. typical low-side drive (sink) characteristics ? high drive (ptxdsn = 1) figure a-2. typical low-side drive (sink) characteristics ? low drive (ptxdsn = 0) 3 measured with v in = v ss . 4 measured with v in = v dd . 5 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 6 all functional non-supply pins are internally clamped to v ss and v dd . 7 input must be current limited to the va lue specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative cl amp voltages, then use the larger of the two values. 8 the reset pin does not have a clamp diode to v dd . do not drive this pin above v dd . typical v ol vs. i ol at v dd = 5v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 01234567 89101112131415 i ol (ma) v ol (v) hot (85c) room (25c) cold (-40c) typical v ol vs. i ol at v dd = 3v 0. 000 0. 200 0. 400 0. 600 0. 800 1. 000 1. 200 1. 400 0. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i ol (ma) v ol (v) hot (85c) room (25c) cold (-40c) typical v ol vs. i ol at v dd = 3v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 01 23 i ol (m a) v ol (v) hot (85c) room (25c) cold (-40c) typical v ol vs. i ol at v dd = 5v 0.0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 0123 i ol (ma) v ol (v) hot (85c) room (25c) cold (-40c)
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 355 figure a-3. typical high-side drive (source) characteristics ? high drive (ptxdsn = 1) figure a-4. typical high-side drive (source) characteristics ? low drive (ptxdsn = 0) typical v dd - v oh vs. i oh at v dd = 5 v 0.0 0.2 0.4 0.6 0.8 0 -1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 i oh (ma) v dd - v oh (v) hot (85c) room (25c) cold (-40c) typical v dd - v oh vs. i oh at v dd =3v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 -1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 i oh (ma) v dd - v oh (v) hot (85c) room (25c) cold (-40c) typical v dd - v oh vs. i oh at v dd = 5v 0.0 0.2 0.4 0.6 0.8 0- 1- 2- 3 i oh (ma) v dd - v oh (v) hot (85c) room (25c) cold (-40c) typical v dd - v oh vs. i oh at v dd =3v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 -1-2-3 i oh (ma) v dd - v oh (v) hot (85c) room (25c) cold (-40c)
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 356 freescale semiconductor a.7 supply current characteristics table a-6. supply current characteristics num c parameter symbol v dd (v) typical 1 1 typicals are measured at 25 c. max 2 2 values given here are preliminary estimates prior to completing characterization. unit 1c run supply current 3 measured at (core clock = 2 mhz, f bus = 1 mhz, blpe mode) 3 all modules except usb and adc active, oscillator disabled (erclken = 0), using external clock resource for input, and does not include any dc loads on port pins. ri dd 51.11.6 ma 30.81.6 2p run supply current 3 measured at (core clock = 8 mhz, f bus = 4 mhz, fbe mode) 54.0 7 ma 33.8 7 3c run supply current 3 measured at (core clock = 48 mhz, f bus = 24 mhz, pee mode) 522 30 ma 321 30 4p stop2 mode supply current ?40 c 25 c 85 c ?40 c 25 c 85 c s2i dd 50.80 3 3 20 a 30.80 3 3 20 a 5p stop3 mode supply current ?40 c 25 c 85 c ?40 c 25 c 85 c s3i dd 50.90 3 3 20 a 30.90 3 3 20 a 6 p adder to stop2 or stop3 for rtc enabled 4 , 25 c 4 most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. wait mode typical is 560 a at 5 v and 422 a at 3 v with f bus = 1 mhz. i srtc 5300 na 3300 na 7p adder to stop3 for lvd enabled (lvde = lvdse = 1) i slvd 5110 a 390 a 8p adder to stop3 for oscillator enabled 5 (erclken = 1 and erefsten = 1) 5 values given under the following conditions: low range operation (range = 0), low power mode (hgo = 0). i sosc 55 a 35 a 9 t usb module enable current 6 i usbe 51.5 ma 10 t usb suspend current 7 i susp 5 270 500 a
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 357 a.8 analog comparator (acmp) electricals a.9 adc characteristics 6 here usb module is enabled and clocked at 48 mhz (usben = 1, usbvren =1, usbphyen = 1 and usbpu = 1), and d+ and d? pull down by two 15.1 k resisters independently. the current consumpti on may be much higher when the packets are being transmitted through the attached cable. 7 mcu enters stop3 mode, usb bus in idle state. the usb susp end current will be dominated by the d+ pullup resister. table a-7. analog comparator electrical specifications num c rating symbol min. typical max. unit 1 ? supply voltage v dd 2.7 ? 5.5 v 2 d supply current (active) i ddac ?2035 a 3 d analog input voltage v ain v ss ? 0.3 ? v dd v 4 d analog input offset voltage v aio ?2040mv 5 d analog comparator hysteresis v h 3.0 6.0 20.0 mv 6 d analog input leakage current i alkg ??1 .0 a 7 d analog comparator initialization delay t ainit ??1 .0 s table a-8. 5 volt 12-bit adc operating conditions characteristic conditions symbol min. typical 1 max. unit comment supply voltage absolute v ddad 2.7 ? 5.5 v delta to v dd (v dd ?v ddad ) 2 v ddad ?100 0 100 mv ground voltage delta to v ss (v ss ?v ssad ) 2 v ssad ?100 0 100 mv ref voltage high v refh 2.7 v ddad v ddad v ref voltage low v refl v ssad v ssad v ssad v input voltage v adin v refl ?v refh v input capacitance c adin ?4.55.5pf input resistance r adin ?3 5k analog source resistance 12 bit mode f adck > 4 mhz f adck < 4 mhz r as ? ? ? ? 2 5 k external to mcu 10 bit mode f adck > 4 mhz f adck < 4 mhz ? ? ? ? 5 10 8 bit mode (all valid f adck )??1 0
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 358 freescale semiconductor figure a-5. adc input impedance equivalency diagram adc conversion clock freq. high speed (adlpc=0) f adck 0.4 ? 8.0 mhz low power (adlpc=1) 0.4 ? 4.0 1 typical values assume v ddad = 5.0 v, temp = 25 c, f adck = 1.0 mhz unless otherwi se stated. typical values are for reference only and are not tested in production. 2 dc potential difference. table a-8. 5 volt 12-bit adc op erating conditio ns (continued) characteristic conditions symbol min. typical 1 max. unit comment + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 359 table a-9. 5 volt 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) characteristic condition s c symbol min. typical 1 max. unit comment supply current adlpc=1 adlsmp=1 adco=1 ti ddad ?133? a supply current adlpc=1 adlsmp=0 adco=1 ti ddad ?218? a supply current adlpc=0 adlsmp=1 adco=1 ti ddad ?327? a supply current adlpc=0 adlsmp=0 adco=1 ti ddad ?0.582 1 ma supply current stop, reset, module off i ddad ?0.011 1 a adc asynchronous clock source high speed (adlpc=0) tf adack 23.35 mhz t adack = 1/f adack low power (adlpc=1) 1.25 2 3.3 conversion time (including sample time) short sample (adlsmp=0) tt adc ?20? adck cycles see table 10.13 for conversion time variances long sample (adlsmp=1) ? 40 ? sample time short sample (adlsmp=0) tt ads ?3.5? adck cycles long sample (adlsmp=1) ? 23.5 ? to t a l unadjusted error 12 bit mode t e tue ? 3.0 10.0 lsb 2 includes quantization 10 bit mode p ? 1 2.5 8 bit mode t ? 0.5 1.0 differential non-linearity 12 bit mode t dnl ? 1.75 4.0 lsb 2 10 bit mode 3 p? 0.5 1.0 8 bit mode 2 t? 0.3 0.5 integral non-linearity 12 bit mode t inl ? 1.5 4.0 lsb 2 10 bit mode t ? 0.5 1.0 8 bit mode t ? 0.3 0.5 zero-scale error 12 bit mode t e zs ? 1.5 6.0 lsb 2 v adin = v ssad 10 bit mode p ? 0.5 1.5 8 bit mode t ? 0.5 0.5
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 360 freescale semiconductor full-scale error 12 bit mode t e fs ? 1 4.0 lsb 2 v adin = v ddad 10 bit mode p ? 0.5 1 8 bit mode t ? 0.5 0.5 quantization error 12 bit mode de q ? ?1 to 0 ?1 to 0 lsb 2 10 bit mode ? ? 0.5 8 bit mode ? ? 0.5 input leakage error 12 bit mode de il ? 1 10 lsb 2 pad leakage 4 * r as 10 bit mode ? 0.2 2.5 8 bit mode ? 0.1 1 temp sensor voltage 25cd v temp25 ?1.396? v temp sensor slope ?40 c ? 25 c dm ?3.266? mv/ c 25 c ? 125 c ? 3.638 ? 1 typical values assume v ddad = 5.0 v, temp = 25 c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 1 lsb = (v refh ? v refl )/2 n 3 monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 4 based on input pad leakage current. refer to pad electricals. table a-9. 5 volt 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) (continued) characteristic condition s c symbol min. typical 1 max. unit comment
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 361 a.10 external oscillator (xosc) characteristics table a-10. oscillator electrical specifications (temperature range = ?40 to 85 c ambient) num c rating symbol min typ 1 1 typical data was characterized at 3.0 v, 25 c or is recommended value. max unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) high range (range = 1) fee or fbe mode 2 high range (range = 1) pee or pbe mode 3 high range (range = 1, hgo = 1) blpe mode high range (range = 1, hgo = 0) blpe mode 2 when mcg is configured for fee or fbe mode, input clock source must be divided using rdiv to within the range of 31.25 khz to 39.0625 khz. 3 when mcg is configured for pee or pbe mode, input clock source must be divided using rdiv to within the range of 1 mhz to 2 mhz. f lo f hi-fll f hi-pll f hi-hgo f hi-lp 32 1 1 1 1 ? ? ? ? ? 38.4 5 16 16 8 khz mhz mhz mhz mhz 2 ? load capacitors c 1, c 2 see crystal or resonator manufacturer?s recommendation. 3? feedback resistor low range (32 khz to 38.4 khz) high range (1 mhz to 16 mhz) r f 10 1 m 4? series resistor low range, low gain (range = 0, hgo = 0) low range, high gain (range = 0, hgo = 1) high range, low gain (range = 1, hgo = 0) high range, high gain (range = 1, hgo = 1) 8 mhz 4 mhz 1 mhz r s ? ? ? ? ? ? 0 100 0 0 0 0 ? ? ? 0 10 20 k 5t crystal start-up time 4 low range, low gain (range = 0, hgo = 0) low range, high gain (range = 0, hgo = 1) high range, low gain (range = 1, hgo = 0) 5 high range, high gain (range = 1, hgo = 1) 5 4 this parameter is characterized and not te sted on each device. proper pc board layout procedures must be followed to achieve specifications. 5 4 mhz crystal. t cstl-lp t cstl-hgo t csth-lp t csth-hgo ? ? ? ? 200 400 5 15 ? ? ? ? ms 6t square wave input clock frequency (erefs = 0, erclken = 1) fee or fbe mode 2 pee or pbe mode 3 blpe mode f extal 0.03125 1 0 ? ? ? 5 16 40 mhz mcu extal xtal crystal or resonator r s c 2 r f c 1
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 362 freescale semiconductor a.11 mcg specifications table a-11. mcg frequency specifications (temperature range = ?40 to 125 c ambient) num c rating symbol min. typical max. unit 1p internal reference frequency ? factory trimmed at v dd = 5 v and temperature = 25 c f int_ft ? 31.25 ? khz 2p average internal reference frequency ? untrimmed 1 1 trim register at default value (0x80) and ftrim control bit at default value (0x0). f int_ut 25 32.7 41.66 khz 3 p average internal reference frequency ? user trimmed f int_t 31.25 ? 39.0625 khz 4 d internal reference startup time t irefst ?60100 s 5? dco output frequency range ? untrimmed 1 value provided for reference: f dco_ut = 1024 x f int_ut f dco_ut 25.6 33.48 42.66 mhz 6 p dco output frequency range ? trimmed f dco_t 32 ? 40 mhz 7c resolution of trimmed dco output frequency at fixed voltage and temperature (using ftrim) f dco_res_t ? 0.1 0.2 %f dco 8c resolution of trimmed dco output frequency at fixed voltage and temperature (not using ftrim) f dco_res_t ? 0.2 0.4 %f dco 9p total deviation of trimmed dco output frequency over voltage and temperature f dco_t ? 0.5 ?1.0 2 %f dco 10 c total deviation of trimmed dco output frequency over fixed voltage and temperature range of 0 ? 70 c f dco_t ? 0.5 1 %f dco 11 c fll acquisition time 2 2 this specification applies to any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (blpe, blpi) to fll enab led (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. t fll_acquire ?? 1ms 12 d pll acquisition time 3 t pll_acquire ?? 1ms 13 c long term jitter of dco output clock (averaged over 2ms interval) 4 c jitter ? 0.02 0.2 %f dco 14 d vco operating frequency f vco 7.0 ? 55.0 mhz 15 d pll reference frequency range f pll_ref 1.0 ? 2.0 mhz 16 t long term accuracy of pll output clock (averaged over 2 ms) f pll_jitter_2ms ? 0.590 5 ? %f pll 17 t jitter of pll output cl ock measured over 625 ns f pll_jitter_625ns ? 0.566 5 ? %f pll 18 d lock entry frequency tolerance 6 d lock 1.49 ? 2.98 % 19 d lock exit frequency tolerance 7 d unl 4.47 ? 5.97 % 20 d lock time ? fll t fll_lock ?? t fll_acquire + 1075(1/ f int_t) s 21 d lock time ? pll t pll_lock ?? t pll_acquire + 1075(1/ f pll_ref) s 22 d loss of external clock minimum frequency ? range = 0 f loc_low (3/5) f int ? ? khz 23 d loss of external clock minimum frequency ? range = 1 f loc_high (16/5) f int ? ? khz
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 363 a.12 ac characteristics this section describes ac timing charac teristics for each peripheral system. a.12.1 control timing 3 this specification applies to any time the pll vco divider or re ference divider is changed, or changing from pll disabled (blpe , blpi) to pll enabled (pbe, pee). if a crystal/r esonator is being used as the reference, this specification assumes it is alread y running. 4 jitter is the average deviation from the programmed fre quency measured over the specified interval at maximum f bus . measurements are made with the device powered by filtered supplie s and clocked by a stable external clock signal. noise injecte d into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 5 jitter measurements are based upon a 48 mhz mcgout clock frequency. 6 below d lock minimum, the mcg is guaranteed to enter lock. above d lock maximum, the mcg will not enter lock. but if the mcg is already in lock, then the mcg may stay in lock. 7 below d unl minimum, the mcg will not exit lock if already in lock. above d unl maximum, the mcg is guaranteed to exit lock. table a-12. control timing num c parameter symbol min typical 1 1 typical values are based on characterization data at v dd = 5.0 v, 25 c unless otherwise stated. max unit 1 bus frequency (t cyc = 1/f bus )f bus dc ? 24 mhz 2 internal low-power oscillator period t lpo 700 1300 s 3 external reset pulse width 2 2 this is the shortest pulse that is guar anteed to be recognized as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. t extrst 100 ? ns 4 reset low drive t rstdrv 66 t cyc ?ns 5 active background debug mode latch setup time t mssu 500 ? ns 6 active background debug mode latch hold time t msh 100 ? ns 7 irq pulse width asynchronous path 2 synchronous path 3 3 this is the minimum pulse width that is guaranteed to pass th rough the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is by passed so shorter pulses can be recognized in that case. t ilih, t ihil 100 1.5 t cyc ??ns 8 kbipx pulse width asynchronous path 2 synchronous path 3 t ilih, t ihil 100 1.5 x t cyc ??ns 9 port rise and fall time low output drive (ptxds = 0),(load = 50 pf) 4 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) high output drive (ptxds = 1), (load = 50 pf) slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 4 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 85 c. t rise , t fall ? ? 40 75 11 35 ns
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 364 freescale semiconductor figure a-6. reset timing figure a-7. irq/kbipx timing a.12.2 timer/pwm (tpm) module timing synchronizer circuits determine the s hortest input pulses that can be re cognized or the fastest clock that can be used as the optional external source to the timer counter. these synchr onizers operate from the current bus rate clock. figure a-8. timer external clock table a-13. tpm input timing num c function symbol min max unit 1 ? external clock frequency f tpmext dc f bus /4 mhz 2 ? external clock period t tpmext 4?t cyc 3 d external clock high time t clkh 1.5 ? t cyc 4 d external clock low time t clkl 1.5 ? t cyc 5 d input capture pulse width t icpw 1.5 ? t cyc t extrst reset pin t ihil irq/kbipx t ilih irq/kbipx t tpmext t clkh t clkl tpmxclk
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 365 figure a-9. timer input capture pulse a.12.3 spi characteristics table a-14 and figure a-10 through figure a-13 describe the timing require ments for the spi system. table a-14. spi electrical characteristic num 1 c characteristic 2 symbol min max unit 1d operating frequency master slave f op f op f bus /2048 dc f bus /2 f bus /4 hz 2d cycle time master slave t sck t sck 2 4 2048 ? t cyc t cyc 3d enable lead time master slave t lead t lead ? 1/2 1/2 ? t sck t sck 4d enable lag time master slave t lag t lag ? 1/2 1/2 ? t sck t sck 5d clock (spsck) high time master and slave t sckh 1/2 t sck ? 25 ? ns 6d clock (spsck) low time master and slave t sckl 1/2 t sck ? 25 ? ns 7d data setup time (inputs) master slave t si(m) t si(s) 30 30 ? ? ns ns 8d data hold time (inputs) master slave t hi(m) t hi(s) 30 30 ? ? ns ns 9 d access time, slave 3 t a 04 0n s 10 d disable time, slave 4 t dis ?4 0n s 11 d data setup time (outputs) master slave t so t so 25 25 ? ? ns ns 12 d data hold time (outputs) master slave t ho t ho ?10 ?10 ? ? ns ns t icpw tpmxchn t icpw tpmxchn
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 366 freescale semiconductor figure a-10. spi master timing (cpha = 0) 1 refer to figure a-10 through figure a-13 . 2 all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. all timing assumes slew rate control disabled and high drive strength enabled for spi output pins. 3 time to data active from high-impedance state. 4 hold time to high-impedance state. sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (modfen = 1, ssoe = 1). 1 2 3 5 6 7 10 11 5 10 4 4
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 367 figure a-11. spi master timing (cpha = 1) figure a-12. spi slave timing (cpha = 0) sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) ss (1) (output) 1. ss output mode (modfen = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. notes: 2 1 3 4 5 6 7 10 11 5 4 sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 6 7 8 9 10 11 5 5 4
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 368 freescale semiconductor figure a-13. spi slave timing (cpha = 1) sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 6 7 8 9 10 11 4 5 5
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 369 a.13 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power s ources other than the normal v dd supply. for more detailed information about program/erase operations. a.14 usb electricals the usb electricals for the s08usbv1 module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit http://www.usb.org. table a-15. flash characteristics num c characteristic symbol min typical 1 1 typical values are based on characterization data at v dd = 5.0 v, 25 c unless otherwise stated. max unit 1 supply voltage for program/erase v prog/erase 2.7 5.5 v 2 supply voltage for read operation v read 2.7 5.5 v 3 internal fclk frequency 2 2 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz 4 internal fclk period (1/fclk) t fcyc 56 . 6 7 s 5 byte program time (random location) (2) t prog 9t fcyc 6 byte program time (burst mode) (2) t burst 4t fcyc 7 page erase time 3 3 these values are hardware state machin e controlled. user code does not n eed to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc 8 mass erase time 2 t mass 20,000 t fcyc 9 c program/erase endurance 4 t l to t h = ?40 c to + 85 c t = 25 c 4 typical endurance for flash is based on the intrinsic bitcell performance. for additional information on how freescale semiconductor defines typical endurance, please refer to engineering bulletin eb619/d, ty p i c a l endurance for nonvolatile memory . 10,000 ? ? 100,000 ? ? cycles 10 data retention 5 5 typical data retention values are based on intrinsic capab ility of the technology measur ed at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale semiconductor defines typical data retention, please refer to engineering bulletin eb618/d, typical data retention for nonvolatile memory. t d_ret 15 100 ? years
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 370 freescale semiconductor if the freescale s08usbv1 implementation has electrical characteristics that deviate from the standard or require additional information, this space woul d be used to communicate that information. 18.5 emc performance electromagnetic compatibility (emc) performance is highly dependant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and char acteristics of external components as well as mcu software operation all pl ay a significant role in emc performance. the system designer can consult fr eescale applications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance specifically targeted at optimizing emc performance. 18.5.1 radiated emissions microcontroller radiated rf emis sions are measured from 150 khz to 1 ghz using th e tem/gtem cell method in accordance with the iec 61967-2 and sae j1752/3 standards. the measurement is performed with the microcontroller installe d on a custom emc evalua tion board while running specialized emc test software. the radiated emissions fr om the microcontroller are measured in a tem cell in two package orientations (north and east). fo r more detailed information concerning the evaluation results, conditions and setup, please refer to the emc evaluation report for this device. the maximum radiated rf emissions of the tested configuration in all or ientations are less than or equal to the reported emissions levels. table a-16. internal usb 3.3v voltage regulator characteristics symbol unit min typ max regulator operating voltage v regin v 3.9 ? 5.5 vreg output v regout v33 . 33 . 6 v usb33 input with internal vreg disabled v usb33in v33 . 33 . 6 vreg quiescent current i vrq ma ? 0.5 ? table 18-8. radiated emissions parameter symbol conditions frequency f osc /f bus level 1 (max) 1 the reported emission level is the value of the maximum em ission, rounded up to the next whole number, from among the measured orientations in each frequency range. unit radiated emissions, electric field v re_tem v dd = 5.0 v t a = +25 o c 0.15 ? 50 mhz 4 mhz crystal 20 mhz bus 7 db v 50 ? 150 mhz 11 150 ? 500 mhz 2 500 ? 1000 mhz ?2 iec level n ? sae level 2 ?
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 371
appendix a electrical characteristics MC9S08JM16 series data sheet, rev. 2 372 freescale semiconductor
MC9S08JM16 series data sheet, rev. 2 freescale semiconductor 373 appendix b ordering information and mechanical drawings b.1 ordering information this section contains ordering numbe rs for MC9S08JM16 series devices. see below for an example of the device numbering system. b.2 orderable part numbering system b.3 mechanical drawings this following pages contain mech anical specifications for mc9s08j m16 series package options. see table b-2 for the document numbers that correspond to each package type. table b-1. device numbering system device number 1 1 see ta b l e 1 - 1 for a complete description of modules included on each device. memory available packages 2 2 see ta b l e b - 2 for package information. flash ram type MC9S08JM16 16,384 1024 48-pin qfn 44-pin lqfp 32-pin lqfp mc9s08jm8 8,192 1024 table b-2. package information pin count type designator document no. 48 qfn gt 98arh99048a 44 lqfp ld 98ass23225w 32 lqfp lc 98ash70029a package designator temperature range family memory status core pb free indicator (c = ?40 c to 85 c) (mc = fully qualified) (9 = flash-based) mc 9 s08 jm 16 c xx e memory size designator (see ta bl e b - 2 )

MC9S08JM16 rev. 2, 5/2008 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purp ose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequentia l or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer app lication by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may o ccur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges th at freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2008. all rights reserved.

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